Stanby mode controller utilizing microprocessor

• US 4,381,552 A
• Filed: 11/18/1980
• Issued: 04/26/1983
• Est. Priority Date: 12/08/1978
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Sharp, Ronald E., Cuadra, Emilio J., Nocilini, John D.
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US06/208,101
• Time in Patent Office: 889 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/707, 365/226, 365/227
• US Class Current: 713/321
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/325 Power saving in peripheral device
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

Logic circuitry in a portable electronic device is combined with the microprocessor to reduce power consumption in the microprocessor and its associated memories during inactive periods of the device, with periodic sampling for inputs from peripherals or received data which would require active operation of the device.

Claims

1. A power conserving circuit for a two-way communications device having high and low power-level operating modes and having two operative states in the higher power mode, the device including a microprocessor, ROM memories, RAM memories and a battery, the circuit comprising in combination:

delay means coupled to receiving and delaying a RAM enabling signal indicative of the operating mode of the device;

first input means coupled to an output of the microprocessor for receiving a signal indicative of one of the two operative states of the device while operating in the high power mode;

clock means for providing a low duty cycle signal;

first logic means coupled to receive the output signals of the first input means, the clock means and the delay means for providing an operating level control signal for portions of the device;

second input means coupled to an output of the microprocessor for providing memory select signals from the microprocessor;

third input means coupled to the battery for providing a power input;

fourth input means coupled to an output of the microprocessor for providing a first memory control signal;

fifth input means coupled to an output of the microprocessor for providing a second memory control signal;

second logic means coupled to receive the output signals of the first logic means and the second, third, and fourth input means for controlling power to ones of said ROM memories;

third logic means coupled to receive the inverted output signals of the second input means and the output signals of the third, fourth and fifth input means and to the first logic means for providing an enabling signal to said RAM memories, the RAM enabling signal also being coupled to the delay means input to provide the mode indicative signal.

2. A power conserving circuit in accordance with claim 1 wherein the operating level control signal from the first logic means is provided in response to at least one of the following input signals:

the clock pulse, the delayed RAM enabling signal, and the operative state indicative signal.

3. A power conserving circuit in accordance with claim 2 and wherein the operative states of the device are the "fetch" and "execute" states.

4. A power conserving circuit in accordance with claim 1 and wherein the second logic means includes a logic gate for providing a power enabling signal in response to the control signal from the first logic means, the memory select signal, and the first memory control signal.

5. A power conserving circuit in accordance with claim 4 wherein the second logic means is also coupled to receive from the microprocessor encoded ROM select signals, and wherein the second logic means includes decoder means enabled by the power enabling signal for decoding the ROM select signals, and includes switching means controlled by the decoded signals for supplying power to respective ones of the ROMs.

6. The power conserving circuit in accordance with claim 1 wherein the third logic means includes a logic gate for providing a first intermediary control signal in response to the input signals from the third, fourth and fifth input means.

7. A power conserving circuit in accordance with claim 6 wherein the third logic means further includes decoder means enabled by the memory select signal for controlling the power level supplied to the RAMs in response to the first intermediate control signal and the operating level control signal.