Binary digit or bit restoration circuit

• US 4,382,298 A
• Filed: 03/27/1981
• Issued: 05/03/1983
• Est. Priority Date: 03/27/1981
• Status: Expired due to Term

• Current Assignee: Telefonaktiebolaget LM Ericsson
• Original Assignee: General Electric Company
• Inventors: Evans, Michael W.
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US06/248,493
• Time in Patent Office: 767 Days
• Field of Search: 371/6, 375/34, 455/63, 455/296
• US Class Current: 714/709
• CPC Class Codes: G11B 20/10 Digital recording or reproducing
• CPC Class Codes: G11B 20/1411 conversion to or from pulse width coding
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence

Abstract

Relatively distorted bits are restored by sampling the bits for a plurality of times during each bit interval. A count of a first binary level of the samples is made for less than the bit interval, so as to eliminate samples at the transitions of the bits. If the count reaches a selected number, a regenerated bit of the first binary level is produced, and if the count does not reach the selected number, a regenerated bit of a second binary level is produced.

Claims

1. An improved circuit for regenerating relatively accurate two-level bit pulses of predetermined period T from distorted two-level bit pulses of said period T comprising:

a. means for sampling the level of said distorted bit pulses a selected plurality of times during each of said periods T;

b. means coupled to said sampling means for counting said samples of a first selected level during the interval beginning a first period of time later than the beginning of each period T and ending a second period of time earlier than the ending of each period T, said counting means being reset prior to each of said intervals, and said counting means being maintained in a fixed condition in response to a predetermined count being reached during each of said intervals;

c. and output means coupled to said counting means for producing a bit pulse of period T having said first selected level in response to at least said predetermined count and for producing a bit pulse of period T having a second selected level in response to less than said predetermined count.

2. The improved circuit of claim 1 wherein said periods of time are both T/N, where N is greater than two.

3. The improved circuit of claim 1 or claim 2 and further comprising clock means that produce pulses whose period is T/R, where R is a multiple of two, and means for applying said clock produced pulses to said sampling means.

4. A circuit for producing relatively undistorted binary digits or bits from relatively distorted input binary digits or bits comprising:

a. a binary counter having N stages, where N is an integer, a first input for said relatively distorted input bits, a second input for clock pulses, and a clearing pulse input;

b. a source of clock pulses having a rate that is at least 2^N+1 times the rate of said relatively distorted input bits;

c. first means for coupling said source of clock pulses to said second counter input for causing said binary counter to count the number of clock pulses applied to said second counter input in response to a relatively distorted input bit of logic 1 applied to said first counter input;

d. second means for applying a clearing pulse to said counter clearing pulse input for the first 2^N+1 /C clock pulses occurring after the beginning of each relatively distorted input binary bit, where C is a number greater than two;

e. third means coupled to the output of at least the most significant count stage of said binary counter for sensing the count therein;

f. fourth means coupling said third means to said first means for passing said clock pulses to said second counter input in response to the absence of a clock count in said most significant stage, and for blocking said clock pulses from said second counter input in response to the presence of a clock count in said most significant stage;

g. and fifth means coupled to said third means for producing relatively undistorted bits of logic 1 in response to the presence of said clock count in said most significant stage, and for producing relatively undistorted bits of logic zero in response to the absence of said clock count in said most significant stage.

5. The circuit of claim 4 wherein said fifth means produces said relatively undistorted bits beginning 2^N+1 /D clock pulses before the end of each relatively distorted input bit, where D is a number that is greater than two.