Large scale, single chip integrated circuit television receiver subsystems

• US 4,383,273 A
• Filed: 12/29/1980
• Issued: 05/10/1983
• Est. Priority Date: 12/29/1980
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Lunn, Gerald K.
• Primary Examiner(s): Murray, Richard
• Application Number:
  US06/220,607
• Time in Patent Office: 862 Days
• Field of Search: 358/188, 358/148, 358/153, 358/158, 455/333
• US Class Current: 348/725
• CPC Class Codes: H04N 5/126 whereby the synchronisation signal indirectly commands a frequency generator
• CPC Class Codes: H04N 5/44 Receiver circuitry for the reception of television signals according to analogue transmission standards H04N5/14 takes precedence

Abstract

A single chip integrated circuit that performs the electronic functions of a monochrome television receiver with the exception of the RF tuner, sound channel, and power output stages. The circuit includes video IF/detector and video processing as well as a two loop horizontal phase locked loop for locking the horizontal flyback to the horizontal sync pulses. In addition, a vertical processing stage is related to the horizontal sync pulses, is included for producing vertical flyback. The circuit operates in a vertical narrow window mode when coincidence occurs between the vertical sync pulses and the output of a vertical countdown circuit to thereby reduce interference from noise and operates in a wide window mode when vertical sync pulses are lost or not yet acquired to allow fast acquisition of the vertical sync pulses.

Claims

1. A television subsystem for performing all of the electronic video processing functions of a television receiver required between the RF tuner and the power output stages of the receiver but for the sound channel, including means for producing horizontal and vertical sync pulses wherein the subsystem is a single integrated circuit.

2. A television subsystem for performing all of the electronic video processing functions of a television receiver required between the RF tuner and the power output stages of the receiver but for the sound channel wherein the subsystem is a single integrated circuit chip, including:

a video amplifier coupled to inputs of the chip for receiving the composite television signal supplied from the RF tuner;

a video detector and video processor for providing luma information at a first output of the chip;

a single processor coupled to an output of said video detector for providing a gain control signal, horizontal and vertical sync signals at respective outputs;

a gated automatic gain control circuit responsive to said gain control signal from said signal processor and both horizontal sync and horizontal flyback signals for providing gain control of said video amplifier;

a horizontal processor circuit coupled to said signal processor and including a two-loop phase locked loop for locking said horizontal flyback signal in relation to said horizontal sync pulses to produce horizontal deflection output signals at a second output of the subsystem; and

a vertical processor circuit which receives an input from said horizontal processor circuit which occurs at a frequency twice the frequency of the horizontal flyback signal and a vertical sync pulse for producing vertical deflection output signals at a third output of the subsystem.

3. A single chip television subsystem integrated circuit for a television receiver, comprising:

a video IF amplifier coupled to inputs of the subsystem for receiving a television composite signal supplied from a RF tuner;

a video detector and video signal processor circuit coupled to the output of said video IF amplifier for providing luma information signals at a first output of the subsystem;

a signal processor circuit for developing both horizontal and vertical sync pulses, said signal processor circuit being coupled to the output of said video detector;

a horizontal signal processor circuit responsive to said horizontal sync pulses and horizontal flyback signals supplied thereto from the horizontal deflection circuitry of the television receiver for producing horizontal deflection output signals at a horizontal line frequency at a second output of the subsystem; and

a vertical signal processor circuit responsive both to said vertical sync pulses and a clocking signal supplied from said horizontal signal processor circuit for producing vertical deflection output signals at a third output of the subsystem.

4. The subsystem of claim 3 wherein:

said clocking signals supplied to said vertical processor circuit from said horizontal processor circuit occur at twice the horizontal line frequency; and

said horizontal processor circuit includes a two loop phase locked loop such that said horizontal flyback signals are locked in relation to said horizontal sync pulses with said phase locked loop including a free running oscillator operating at twice said horizontal line frequency, said frequency thereof being varied such that the output from said oscillator occurs in relation to said horizontal sync pulses.

5. The subsystem of claim 4 wherein said vertical processor includes:

a window control circuit; and

a countdown circuit coupled with said window control circuit for receiving said vertical sync pulses and said clocking signals such that the subsystem operates in a vertical narrow window mode when coincidence occurs between said vertical sync pulses and a reset window pulse produced by said countdown circuit, the subsystem operating in a wide window mode in the absence of said coincidence until such time said coincidence is reestablished, the gain of one of said two loops of said horizontal phase locked loop being varied in accordance with each mode of operation.

6. In a television receiver including a RF tuner, sound channel, power output driver stages for driving a cathode ray tube, the improvement comprising the partitioning of a subsystem of the receiver wherein a single chip integrated circuit is provided to produce the video electronic functions of the television receiver required between the RF tuner and power output driver stages thereof including processing means for producing horizontal and vertical sync pulses.

7. In a television receiver including a RF tuner, sound channel, power output stages for driving a cathode ray tube, the improvement comprising the partitioning of a subsystem of the receiver wherein a single chip integrated circuit is provided to produce the video electronic functions of the television receiver required between the RF tuner and the power output driver stages, the subsystem including:

a video IF amplifier coupled to inputs of the chip for receiving the output from the RF tuner;

a video detector and video signal processor coupled to an output of said IF amplifier for providing luma signal information to the tube at a first output of the chip;

a signal processor for providing horizontal and vertical sync pulses at respective outputs, said signal processor being coupled to an output of said video detector;

a horizontal processor responsive to said horizontal sync pulses and to generated horizontal flyback signals supplied thereto from the horizontal deflection circuit of the television receiver to phase lock said horizontal flyback signals to said horizontal sync pulses for providing horizontal deflection signals to said horizontal deflection circuit at a second output of the subsystem; and

a vertical processor receiving said vertical sync pulses and input control signals from said horizontal processor which operates in a first or a second mode depending on said vertical sync pulses occurring in coincidence with a coincidence signal generated from said input control signals for providing vertical deflection signals to vertical deflection circuit for the television receiver to provide vertical flyback periods.

8. A monolithic integrated circuit for use in a television receiver to perform all of the video processing functions of the television receiver including a video detector circuit wherein video signal information is detected and separated from a composite television signal supplied to the television receiver without requiring an external tuned circuit coupled to said video detector circuit.

9. A monolithic integrated circuit for use in a television receiver to perform all of the video processing function of the television receiver between the RF tuner and the power output stages of the receiver, said circuit comprising a video detector circuit for detecting the composite video information signal, said video detector circuit being formed totally within the integrated circuit.

10. In a television receiver, an integrated circuit for performing the electronic video processing functions of the television receiver, said integrated circuit including a video detector circuit formed in the integrated circuit for detecting the video composite signal, said video detector circuit requiring no external tuned tank circuit to be coupled therewith.