Idle time slot seizure and transmission facilities for loop communication system

• US 4,383,315 A
• Filed: 07/20/1981
• Issued: 05/10/1983
• Est. Priority Date: 07/20/1981
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Inventors: Torng, Hwa C.
• Primary Examiner(s): Olms, Douglas W.
• Application Number:
  US06/284,738
• Time in Patent Office: 659 Days
• Field of Search: 370/89, 370/86, 370/93, 370/95, 370/85, 370/92, 340/825.05, 340/825.5, 340/825.51
• US Class Current: 370/452
• CPC Class Codes: H04L 12/43 with synchronous transmission, e.g. time division multiplex [TDM], slotted rings
• CPC Class Codes: H04L 12/64 Hybrid switching systems
• CPC Class Codes: H04M 11/068 using time division multiplex techniques; integrated services digital networks H04Q11/0428
• CPC Class Codes: H04M 9/025 Time division multiplex systems, e.g. loop systems

Abstract

A time division multiplex loop communication system for voice and data is disclosed with multiaccess time slot seizure and data transmission capability from all station nodes without changing the idle, nonreserved, status of the seized time slot. A method and station node apparatus sends bursty data packets from a node when a time slot is not busy serving a longer duration voice telephone call. The apparatus eliminates the need for inefficient time slot request, acknowledgement and reservation procedures which require several TDM frames to complete and which are typically longer in duration than the bursty data packet to be transmitted. All stations have access to all time slots for bursty data transmission under control of loop interface circuitry which statistically ensures the successful data transmission from all sending nodes. The interface circuitry includes input and output buffers, slot and bit identification circuitry, bit stream retard circuitry, output selector circuitry, bypass decision circuitry, and data and voice insertion control circuitry comprising a slot decision control circuit, a seizure timing circuit and an acknowledgment check circuit.

Claims

1. A method for controlling a seizure of an idle one of a plurality of time slots in a time division multiplex loop communication system to transmit a packet of data information bits over a loop transmission path thereof and in that idle time slot while it retains its idle status, each of said time slots comprising at least one busy-idle status bit and information bits, each said status bit being marked busy for the duration of a call served by the respective time slot and being marked idle during intercall periods, said method comprising

storing a packet of data information bits,

examining said status bit of each one of said slots to identify the idle or busy status thereof,

seizing an idle one of said time slots in response to said examining identifying said idle one of said time slots, and

transmitting over said loop transmission path in said idle one of said time slots an idle status bit and the stored said packet of data information bits.

2. The invention of claim 1 wherein

said seizing step comprises

generating a timing interval which a station waits before seizing said idle one of said time slots, and

signaling the expiration of said timing interval to effect a seizure of said idle one of said time slots.

3. In a time division loop communication system having a plurality of station ports disposed along a loop transmission means with time division multiplexing including a plurality of successively recurring time frames each of which comprises a plurality of time slots, each one of said time slots transmitting at least one bit for indicating the reserved or free status of said one time slot and digitally encoded information bits, and

each one of said ports comprising

means responsive to a receipt of a time slot free indicating bit of said one of said time slots and to a slot request signal for controlling a seizure of said one of said time slots,

means storing station information bits, and

means activated by said controlling means for transmitting from said one port onto said loop transmission means said free indicating bit and said station information bits in a seized one of said time slots.

4. The invention of claim 3 wherein

said storing means comprises a slot output buffer means for storing data information bits, and

said transmitting means comprises an output bit stream generator means cooperating with said buffer means and being responsive to control signals from said controlling means for generating on said loop transmission means said free indicating bit and said data information bits in said seized one of said time slots.

5. The invention of claim 4 wherein

said controlling means comprises

a slot seizure timing circuit for generating a time interval which said one station port waits before a generation of a slot seizure control signal, and

a slot decision control circuit responsive to a receipt of said time slot free indicating bit of said one of said time slots, said slot seizure request signal, and a generated slot seizure control signal for signaling said output bit stream generator means to generate said free indicating bit and said data information bits in said seized one of said time slots.

6. The invention of claim 5 wherein

said slot seizure timing circuit comprises

counter means settable to a predetermined count and being responsive to a receipt of clock signals for decrementing said predetermined count, and

means responsive to a prescribed count of said counter means for generating said slot seizure control signal.

7. The invention of claim 6 wherein

said counter means comprises

a counter device settable to a count estimate of the number of other of said station ports ready to seize time slots for transmission of data, said device being responsive to a receipt of clock signals for decrementing the count thereof, and

counter apparatus responsive to a receipt of count signals from said counter device and to a range count signal for setting a count defining said time interval for said slot seizure timing circuit.

8. The invention of claim 7 wherein

said counter apparatus is responsive to clock signals for decrementing the set count defining said time interval, and

said generating means comprises a zero detect arrangement responsive to a zero count of said counter apparatus for generating said slot seizure control signal.

9. The invention of claim 8 wherein

said slot decision circuit further comprises

circuitry cooperating with said slot decision control circuit for checking for a receipt of a signal acknowledging a reception of said data information bits.

10. The invention of claim 9 wherein

said checking circuitry comprises

a timer counter settable to a predetermined count under control of said slot decision control circuit to define a prescribed interval within which said acknowledging signal is to be received,

means for decrementing said predetermined count of said timer counter, and

a zero detect means responsive to a zero count of said timer counter for incrementing said count of said counter device to reflect a nonreceipt of said acknowledging signal.

11. In a time division multiplex system having a plurality of station nodes located along a unidirectional loop transmission path and a recurring frame of time slots each of which comprises at least one busy-idle status bit and information bits, each said status bit being marked busy for the duration of a call served by the respective time slot and being marked idle during intercall period,

each of said station nodes including

as output buffer means for storing a packet of data, and

means responsive to a receipt of an idle status bit for one of said time slots on said loop transmission path for seizing said one of said time slots to control an insertion of the stored data packet from said buffer means into said idle time slot for transmission over said loop transmission path with said idle status bit of said one of said time slots to a destination one of said station nodes during the idle status of said one of said time slots.

12. The invention of claim 11 wherein said seizing and data insertion control means comprises

a slot decision circuit responsive to a slot seizure request signal and a receipt of said idle status bit for selectively controlling an insertion of said stored data packet from said output buffer means to said idle time slot for transmission over said loop transmission path with said idle status bit of said one of said slots.

13. The invention of claim 12 wherein said slot decision circuit comprises

a slot decision control means operable for generating a slot seizure signal,

seizure timing means controlled by said decision control means for generating a slot seizure enable signal at the termination of a timing interval that defines a time which said decision control circuit waits before generating a slot seizure signal, and

said decision control means being responsive to a receipt of a slot seizure request signal, said idle status bit and said slot seizure enable signal for generating said slot seizure signal.

14. The invention of claim 13 further comprising

means controlled by said slot decision control means for generating a timed interval within which a signal should be received by said slot decision circuit acknowledging a receipt of said data packet at said destination one of said station nodes.

15. The invention of claim 14 further comprising

means responsive to an expiration of said timed interval indicating a nonreceipt of said acknowledging signal for controlling said seizure timing means to effect an increase in the duration of said timing interval.

16. The invention of claim 12 further comprising

means activated by said slot decision circuit and said output buffer for generating a bit stream in said one of said time slots, said bit stream comprising said idle status bit and said data packet stored in said output buffer means.

17. The invention of claim 16 wherein

said bit stream generating means comprises configuration gate devices for logically combining said idle status bit of said one time slots sequentially with said data packet stored in said output buffer means.

18. In a time division multiplex system having a plurality of station nodes located along a unidirectional loop transmission path and a recurring frame of time slots each of which comprises at least one busy-idle status bit and information bits, each said status bit being marked busy for the duration of a call served by the respective time slot and being marked idle during intercall periods,

each of said station nodes comprising

input buffer means for sequentially receiving for storage time slot status and information bits from an incoming link of said loop transmission path,

means for retarding by at least one bit time the received time slot status and information bits on said incoming link,

means cooperating with said retarding means for identifying each time slot of said frame and said status bit thereof,

output buffer means for storing voice/data information bits,

another output buffer means for storing a packet of data information bits, and

means responsive to a channel reservation request signal for controlling an insertion of the voice/data information bits stored in said output buffer means with a marked busy bit into an identified one of said time slots, and

data insertion control means responsive to the time slot idle status bit stored in said input buffer means and to a slot seizure request signal for controlling an insertion of said packet of data information bits with said idle status bit into an idle identified one of said time slots.

19. The invention of claim 18 wherein said voice/data information bits insertion controlling means comprises

channel decision circuit means responsive to said channel reservation request signal and to information bits stored in said input buffer means for controlling a reservation of said prescribed one of said time slots as a voice/data communication channel,

reserved channel register means for storing the identity of the reserved one of said time slots, and

channel matching means for matching the time slot identity stored in said register means with a received current time slot identity for effecting an insertion of said voice/data information bits stored in said output buffer means with said marked busy bit into said reserved one of said time slots.

20. The invention of claim 19 wherein said identifying means comprises

a slot counter for identifying the presently occurring time slot at said each station node,

a status bit circuit for identifying the busy-idle status bit of the presently occurring time slot at said each station node, and

clock means driven by said retarding circuit for controlling the identifications by said slot counter and said status bit circuit.

21. The invention of claim 18 further comprising

means activated by said data insertion control means, and identifying means and said output buffer means for generating an idle status bit of said idle identified one of said time slots and followed by a packet of information bits in said idle identified one of said time slots.

22. The invention of claim 21 wherein said data insertion control means comprises

a slot decision circuit controlled by said input buffer means and said identifying means and being responsive to said slot seizure request signal for controlling an activation of said generating means.

23. The invention of claim 22 wherein said slot decision circuit comprises

a slot decision control means operable for generating a slot seizure signal,

seizure timing means controlled by said decision control means for generating a timing interval that defines a time which said decision control waits before generating a slot seizure signal, and

said decision control means being responsive to a receipt of a slot seizure request signal, said idle status bit of said idle identified one of said time slots and to a signal specifying an expiration of said timing interval for generating said slot seizure signal.

24. The invention of claim 23 wherein said slot decision circuit further comprises

means controlled by said slot decision control means for generating a timed interval within which an acknowledgment signal should be received in said idle identified one of said time slots by said slot decision circuit acknowledging a receipt of said data packet at destination one of said station nodes.

25. The invention of claim 24 further comprising

means responsive to an expiration of said timed interval indicating a nonreceipt of said acknowledgment signal for controlling said seizure timing means to effect an increase of said timing interval.

26. The invention of claim 23 wherein

said slot seizure timing circuit comprises

counter means settable to a predetermined count and being responsive to a receipt of clock signals from said slot decision control means for decrementing said predetermined count, and

means responsive to a prescribed count of said counter means for generating said signal specifying an expiration of said timing interval.

27. The invention of claim 26 wherein

said counter means comprises

a counter device settable to a count estimate of the number of the said station nodes ready to seize time slots for transmission of data, said device being responsive to said receipt of said clock signal for decrementing the count thereof, and

counter apparatus responsive to a receipt of count signals from said counter device and to a range count signal for setting a count defining said timed interval for said slot seizure timing circuit.

28. The invention of claim 27 wherein

said counter apparatus is responsive to a receipt of clock signals for decrementing the set count defining said timed interval, and

said expiration signal generating means comprises a zero detect arrangement responsive to a zero count of said counter apparatus for generating a slot seizure enable signal.

29. A time division multiplexed loop communication system for providing integrated voice and data services in a plurality of time slots each of which has a reserved/free bit and comprising a plurality of station ports, each of which comprises

means for examining the reserved/free status bits of each of said time slots,

means controlled by said examining means for reserving free time slots as communication channels in said system to transmit digitally encoded data and voice samples,

means controlled by said examining means for seizing free one of said time slots, and

means activated by said seizing means for generating digitally encoded packets of data information and a free status bit in said free one of said time slots.

30. The invention of claim 29 wherein

said seizing means comprises

means activated for delaying the seizing of a free one of said time slots for a prescribed interval.