Time warp signal recognition processor for matching signal patterns

• US 4,384,273 A
• Filed: 03/20/1981
• Issued: 05/17/1983
• Est. Priority Date: 03/20/1981
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Inventors: Ackland, Bryan D., Burr, David J., Weste, Neil H. E.
• Primary Examiner(s): Boudreau, Leo H.
• Application Number:
  US06/245,952
• Time in Patent Office: 788 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 364/131, 364/133, 364/136, 364/515, 364/704, 364/513, 340/146.2, 340/146.3 MA, 340/146.3 H, 340/146.3 R, 340/146.3 Q, 179/1 SB, 179/1 SD
• US Class Current: 382/215
• CPC Class Codes: G06V 10/754 involving a deformation of the sample pattern or of the reference pattern; Elastic matching
• CPC Class Codes: G10L 15/12 using dynamic programming techniques, e.g. dynamic time warping [DTW]

Abstract

Known signal processors for matching signal patterns commonly compare an unknown signal with one of a set of reference signals. Various comparison techniques are known. One comparison technique for solving a parenthesization problem includes an orthogonal array of interconnected cells which are adapted for dynamic programming and for extending data and control information in a generally left-to-right direction as well as in a bottom-to-top direction. For solving a pattern matching problem, known arrangements for extending control information in a generally left-to-right or bottom-to-top direction do not appear to be satisfactory. The disclosed signal processor for matching signal patterns and for dynamically time warping an unknown input signal with a reference input signal generates a measure of the correspondence between the input signals. In generating the correspondence measure, the processor includes an arrangement for controlling all processor cells on a predetermined diagonal of the array of cells. Thereby all cells coupled to the diagonal can operate in parallel to increase and improve the efficiency of the signal processor. The processor also includes an arrangement for controlling all processor cells on each diagonal of the array of cells. As a result, not only can all cells on each diagonal operate in parallel but also each of the plurality of diagonals can operate in parallel for processing the same or different sets of input signals. Thereby, a still further increase in the efficiency of the signal processor obtains.

Claims

1. A method for matching signals, said method including the step of

extending an unknown input signal and a reference input signal through an orthogonal array of processor cells and characterized in that said method further comprises the steps of:

time warping one input signal with respect to the other input signal;

processing said wrapped input signals in processor cells, said cells being coupled to a predetermined diagonal of said array;

controlling said processing by having all cells coupled to said diagonal of said array concurrently processing said input signals; and

generating during said processing a measure of the correspondence between said input signals.

2. The method for matching signals defined in claim 1 further comprises the steps of:

controlling the parallel processing of each of a plurality of respective diagonals of said array whereby said respective diagonals concurrently process respective input signals.

3. In a signal recognition system, a signal processor including an array of cells, said cells adapted for processing an input signal according to a predetermined criteria and characterized in that said signal processor further comprises

(a) means for time warping an unknown input signal and a reference input signal,

(b) means responsive to said warped signals for generating a measure of the correspondence between said input signals, said generating means including means for controlling the parallel processing of a plurality cells, said plurality of cells being coupled to a predetermined diagonal of said array of cells, and

(c) means for extending said correspondence measure to an output terminal.

4. The signal processor defined in claim 3 wherein said parallel processing control means further includes

(d) means for controlling the parallel processing of cells on a plurality of respective predetermined diagonals of said array of cells.

5. A signal processor including an array of processor cells, means for extending an input signal through said cells to an output terminal and characterized in that said signal processor further comprises pattern matching means, said pattern matching means including:

(a) first means for comparing a first unknown input signal and a first reference input signal,

(b) first means for time warping either of said first input signals with respect to the other of said first input signals, and

(c) diagonal control means coupled to said first time warping means for controlling cells on a first predetermined diagonal of said array of cells, said diagonal controlling means including means for the parallel processing of said signals to be compared.

6. The signal processor defined in claim 5 wherein said pattern matching means further includes:

means for providing an optimal time warp path through said array of processor cells.

7. The signal processor defined in claim 5 wherein said pattern matching means further includes:

means responsive to said diagonal control means for measuring a correspondence between said input signals and

means for extending said correspondence measure to an output terminal.

8. The signal processor defined in claim 6 wherein said pattern matching means further includes:

means responsive to said diagonal control means for measuring a correspondence between said input signals and

means for extending said correspondence measure to an output terminal.

9. The signal processor defined in claim 5 wherein said pattern matching means further includes:

(d) second means for comparing a second unknown input signal and a second reference input signal,

(e) second means for time warping either of said second input signals with respect to the other of said second input signals,

(f) said diagonal control means coupled to said second time warping means for controlling cells on a second predetermined diagonal of said array of cells.

10. The signal processor defined in claim 9 wherein said diagonal control means further includes:

(g) means for parallel processing such that not only do all cells on said first diagonal parallel process said first input signals to be compared and all cells on said second diagonal parallel process said second input signals to be compared but also said first diagonal processing occurs substantially concurrent and in parallel with said second diagonal processing.