Current mirror digital to analog converter

• US 4,384,274 A
• Filed: 09/02/1980
• Issued: 05/17/1983
• Est. Priority Date: 06/22/1979
• Status: Expired due to Term

• Current Assignee: American Microsystems Limited Incorporated (ON Semiconductor Corporation)
• Original Assignee: American Microsystems Limited Incorporated (ON Semiconductor Corporation)
• Inventors: Mao, Roger A.
• Primary Examiner(s): Sloyan, T. J.
• Application Number:
  US06/183,171
• Time in Patent Office: 987 Days
• Field of Search: 340/347 M, 340/347 DA, 330/288
• US Class Current: 341/135
• CPC Class Codes: H03M 1/16 with scale factor modification, i.e. by changing the amplification between the steps H03M1/141 takes precedence
• CPC Class Codes: H03M 1/74 Simultaneous conversion

Abstract

An integrated circuit digital to analog converter comprised of MOS current mirrors and utilizing additional MOS devices to provide transmission gates and control means. Each transmission gate 36 is connected to a source of digital data to be converted and the mirroring device for each transmission gate 36 has a channel width with some predetermined proportional relationship to the channels of input transistors 12 and mirroring output MOS transistors 14 to 44 with the input transistor 12 connected to a constant current source, the total output mirroring current of the output mirroring transistors is in quantized analog form and varies according to the cumulative currents from the mirroring MOS transistors as the transistors are activated. The invention may be embodied in linear multiplying, non-linear and companding converters.

Claims

1. A digital to analog converter making use of current mirror transistors comprising

a first reference transistor connected to conduct a first reference current;

a selected number of first transistors, each connected to conduct, when activated, a current of a unique value in proportion to said first reference current;

first means to activate one or more of said selected number of first transistors to conduct respective currents of said unique values;

current mirror means to form a sum of the currents conducted by said selected number of first transistors, when activated, and to produce a first summed current which is a selected proportion of said sum;

a second reference transistor for conducting a second reference current;

a selected number of second transistors each connected to conduct, when activated, a current of a unique value in proportion to said second reference current;

second means to activate one or more of said selected number of second transistors to conduct respective currents of said unique values; and

means to form a sum of said first summed current and the current conducted by said selected number of second transistors, when activated, to produce an output current proportional to a selected digital input signal.

2. Structure as in claim 1 wherein said first and second means to activate are controlled by a digital code word and wherein said output signal from said converter is proportional to the magnitude of said digital code word.

3. A digital to analog converter comprising:

a constant current supply;

a constant voltage supply;

a series of N input terminals for receiving N digital input signals, where N is a selected positive integer;

a reference terminal;

an output terminal for providing an analog output current;

a current mirror comprising a first MOS transistor capable of passing a first selected current, a second MOS transistor connected to pass a current proportional to said first current, and a control element for turning on and off said second transistor, said current mirror having a first lead connected to said constant current supply, second and third leads connected to said reference terminal, and a fourth lead on which said current mirror provides said current proportional to said first selected current through said first lead of said current mirror;

a first series of M FETs of a first conductivity type each having a gate, a source, a drain, and a channel between said source and drain, each said source of said first series of FETs being connected in common to said reference terminal and each said drain of said first series of FETs being connected in common, where M is a second selected integer;

a first series of M switch means, each having an input lead connected to said current supply, a control lead connected to a respective one of said series of N input terminals, and an output lead connected to said gate of a respective one of said first series of M FETs, whereby said first series of M switch means controls a first current through said first series of M FETs;

an FET of a second conductivity type opposite said first conductivity type, having a gate, a source, and a drain, said source being connected to said voltage supply and said drain and said gate being connected to said fourth lead of said current mirror;

a second series of R FETs of said second conductivity type each having a gate, a source, a drain, and a channel between said source and drain, each said source of said second series of R FETs being connected in common to said voltage supply, and each said drain of said second series of R FETs connected in common to said output terminal, where R is a third selected integer;

a second series of R switch means each having an input lead connected to said fourth lead of said current mirror, a control lead connected to a respective one of said series of N input terminals, and an output lead connected to said gate of a respective one of said second series of R FETs, whereby said second series of R switch means controls a second current through said second series of FETs; and

current scaling means for adding a selected fraction of said first current to said second current and providing a third current equal to the sum of said first current and said second current at said output terminal, wherein said third current is defined by the value of said N digital input signals.

4. The structure of claim 3 wherein said

current scaling means has first and second leads connected to said voltage supply, a third lead connected to said drains of said first series of M FETs for providing a current to the drains of said first series of M FETs, and a fourth lead for providing a current to said output terminal proportional to the current through said third lead of said current scaling means.

5. The structure of claim 3 including

means for providing digital input signals comprising least significant to most significant binary signals;

means for applying each of said binary signals to a corresponding one of said series of N input terminals and through one switch of said first and said second series of switch means to the gate of the corresponding one of said first and second series of FETs.

6. The structure of claim 3 wherein

said current mirror comprises a pair of FETs of said first conductivity type each having a gate, source and drain, said gates and a first one of said drains being connected to said first lead to said current supply, said sources being connected to said second and third leads, and having a second one of said drains connected to said fourth lead of said current mirror.

7. The structure of claim 3 wherein

said current scaling means comprises two FETs having sources connected to said voltage supply, gates and a first drain connected to said drains of said first series of FETs, and a second drain connected to said output terminal.

8. The structure of claim 5 wherein the channel of each FET in said first and second series of FETs is one-half the width of the channel of an adjacent FET within said series, whereby each FET of said first and second series of FETs conducts a current whose magnitude is defined by the location of the FET in said first and second series of FETs and by the state and significance of the binary signal corresponding to said FET.

9. The structure of claim 8 wherein said N input terminals are numbered from n=0 to N-1 for least to most significant digital input signals, respectively, where n is an integer given by 0≦

n≦

N-1, said digital input signals each have a value V_n equal to 0 or 1;

said constant current is denominated I_ref ; and

said output current is equal to ##EQU15##

10. A digital to analog converter comprising:

a constant current supply;

a constant voltage supply;

a plurality of N input terminals for receiving N digital input signals, where N is a positive integer;

a ground terminal;

an output terminal for providing an analog signal;

a first current supply FET of a first conductivity type having a drain and a gate connected in common to said current supply, a source connected to said ground terminal, and a channel region between said source and drain;

a first series of current switching first conductivity type FETs and corresponding switches, said first series of FETs each having a gate, a source, a drain and a channel region between said source and drain, wherein the width of said channel region is a selected fraction of the width of said channel of said first current supply FET, said sources of said first switching FETs being connected to said ground terminal, and said drains of said first switching FETs being connected to a node, said corresponding switches having a control lead connected to a corresponding one of said N input terminals, an input lead connected to said current source, and an output lead connected to said gate of that one of said first series of current switching first conductivity type FETs to which said switch corresponds, whereby digital signals applied to said control leads cause each said switching FET to conduct or not to conduct a current to said common node, said current being in proportion to the width of the channel region of said FET, the currents through said first series of current switching first conductivity type FETs forming a first sum of currents;

a first current supply mirroring FET of said first conductivity type having a gate connected to said current supply, a source connected to said ground terminal, and a drain through which said first current supply mirroring FET provides a current proportional to current through said first current supply FET;

a second current supply mirroring FET, of a second conductivity type which is opposite to said first conductivity type, having a source connnected to said voltage supply, having a channel, and having a gate and a drain connected in common to said drain of said first current supply mirroring FET, whereby the same value of current flows through said second current supply mirroring FET as through said first current supply mirroring FET;

a second series of current switching second conductivity type FETs and corresponding switches, said second series of current switching second conductivity type FETs each having a gate, a source, a drain and a channel region between said source and drain, wherein the width of said channel region is a selected fraction of the width of said channel region of said second current supply mirroring FET, said sources of said second series of current switching second conductivity type FETs being connected in common to said voltage supply and said drains of said second series of current switching second conductivity type FETs being connected in common and supplying a second sum of currents to said output terminal, said corresponding switches each having a control lead connected to a corresponding one of said N input terminals, an input lead connected to said drain of said second current supply mirroring FET, and having an output lead connected to said gate of the switching second conductivity type FET to which said switch corresponds; and

current scaling means including a first scaling FET of said second conductivity type having a source connected to said voltage supply, a gate and a drain connected in common to said node, and a channel region between said gate and drain, whereby said first sum of currents through said first series of current switching first conductivity type FETs flows through said first scaling FET, said current scaling means further including a second scaling FET of said second conductivity type having a channel region whose width is a selected fraction of the width of said channel region of said first scaling FET, said second scaling FET having a source connected to said voltage supply, a gate connected to said gate of said first scaling FET, and a drain connected to said output terminal, whereby said second scaling FET conducts a current to said output terminal in the same proportion to the current through said first scaling FET as the proportion of the channel width of said second scaling FET to the channel width of said first scaling FET, whereby said current from said second scaling FET and said second sum of currents together form an output signal which is defined by said N digital input signals.

11. The converter of claim 10 wherein said selected fractions for the widths W of said switching FETs are interrelated by the formula W=2 exp(rem n/s), where said switching FETs are numbered n=0 to N-1 corresponding to the least to most significant of said N digital inputs respectively, s=N/2, and "rem" means integers remaining after an integer quotient.

12. The converter of claim 10 wherein said selected fractions for the widths W of said switching FETs are interrelated by the formula W=2 exp(rem n/s), where said switching FETS are numbered n=0 to N-1 corresponding to the least to most significant of said N digital inputs respectively, s=(N-1)/2, and "rem" means integers remaining after an integer quotient.

13. The converter of claim 10 wherein the product of channel widths of said first scaling FET and the member of said second series of switching FETs corresponding to the least significant digital input to said second series is twice the product of channel widths of said second scaling FET and the member of said first series of switching FETs corresponding to the most significant digital input to said first series.