Dust control apparatus with cleaning control circuit

• US 4,384,874 A
• Filed: 04/10/1981
• Issued: 05/24/1983
• Est. Priority Date: 04/10/1981
• Status: Expired due to Fees

• Current Assignee: Donald P. Dattilo
• Original Assignee: Donald P. Dattilo
• Inventors: Dattilo, Donald P.
• Primary Examiner(s): LACEY, DAVID LYNN
• Application Number:
  US06/252,856
• Time in Patent Office: 774 Days
• Field of Search: 55/96, 55/273, 55/286, 55/287, 55/302, 55/385 D, 210/411, 210/412, 299/12, 175/66, 307/223 R, 307/269, 307/480, 307/596, 328/72, 328/103
• US Class Current: 96/426
• CPC Class Codes: B01D 46/04 Cleaning filters
• CPC Class Codes: B01D 46/71 with pressurised gas, e.g. pulsed air
• CPC Class Codes: E21B 21/015 Means engaging the bore entrance, e.g. hoods for collecting dust

Abstract

This disclosure relates to a dust control apparatus including mobile drilling rig having a peripheral skirt which collects dust during a drilling operation and delivers the same to a dust collector having a chamber housing and a plurality of filters, each filter being cleaned by a high pressure air line through an appropriate solenoid valve and a sequencing control circuit for operating the solenoid valves to sequentially deliver high pressure air into the filters so that the dust collected thereon can be blown therefrom dropping into the chamber and outwardly therefrom through a discharge opening.

Claims

1. Dust control apparatus comprising means for collecting dust as it is being formed by a drill adjacent an associated bore hole, means for receiving dust from said dust collecting means, said dust receiving means including a chamber, filter means in said chamber for collecting dust received therein, air pressure means connected to said filter means for delivering air pressure to said filter means for cleaning the dust therefrom, circuit means for selectively controlling the sequential operation of said air pressure means to deliver same to the filter means at predetermined intervals to clean the dust therefrom at such predetermined intervals, discharge means for removing dust from said chamber, said filter means comprising a plurality of filters positioned in said chamber, said apparatus further including an electronically controlled valve positioned and arranged between each of said filters and said air pressure means for delivering air pressure from said air pressure means to each of said filters, said circuit means including oscillator means for developing spaced predetermined pulses, said circuit means further including counter means receiving said predetermined pulses and developing reoccurring groups of coded pulses corresponding in number to the plurality of filters, said circuit means also including decoder means for developing a single output drive pulse from each group of coded pulses corresponding to the particular filter to be cleaned, and said circuit means including means for delivering each particular output drive pulse to one of said electronically controlled valves for delivering air pressure from said air pressure means to one of said filters, said circuit means including timing means for developing on-time pulses each of a predetermined duration, said circuit means including means for controlling the delivery time of the output drive pulse and said circuit means further including means for varying the spacing between each of said on-time pulses in relation to the pressure supplied by said pressure means.

2. The dust control apparatus as defined in claim 1 wherein said circuit means includes means for combining a stored capacitive charge with said decoder means to provide an unusually strong means of energizing said electronically controlled valve.

3. The dust control apparatus as defined in claim 2 wherein said circuit means includes means for varying the time spacing between said predetermined pulses.

4. The dust control apparatus as defined in claim 2 wherein said circuit means includes means for selectively resetting said counter means depending upon a preselected number of said groups of coded pulses developed by said counter means.

5. The dust control apparatus as defined in claim 2 wherein said circuit means includes means for selectively resetting said counter means depending upon a preselected number of said groups of coded pulses developed by said counter means, said circuit means includes switch means for selectively establishing said predetermined number within the total number of said filters, said switch means including a plurality of gate means having input means connected to said counter means for reading the groups of coded pulses, each gate means having an output indicative of a particular one of said groups, a switch arm selectively connected to any one of said gate means outputs, and said switch arm also being connected to a reset input of said counter means.

6. The dust control apparatus as defined in claim 1 wherein said circuit means includes means for varying the predetermined spacing between said predetermined pulses.

7. The dust control apparatus as defined in claim 1 wherein said circuit means includes means for selectively resetting said counter means depending upon a preselected number of said groups of coded pulses developed by said counter means.

8. The dust control apparatus as defined in claim 1 wherein said circuit means includes means for selectively resetting said counter means depending upon a preselected number of said groups of coded pulses developed by said counter means, and said circuit means also includes switch means for selectively establishing said predetermined number within the total number of said filters.

9. The dust control apparatus as defined in claim 1 wherein said delivering means includes a transistor connected to each electronically controlled valve, a power source also connected to each electronically controlled valve, and said circuit means includes means between said power source and each transistor for preventing reverse voltage from damaging said transistor.

10. The dust control apparatus as defined in claim 1 wherein said circuit means includes means for selectively resetting said counter means depending upon a preselected number of said groups of coded pulses developed by said counter means, said circuit means includes switch means for selectively establishing said predetermined number within the total number of said filters, said switch means includes a plurality of gate means having input means connected to said counter means for reading the groups of coded pulses, each gate means having an output indicative of a particular one of said gate means outputs, and said switch means includes a switch arm connected to a reset input of said counter means.