Dual species ion implantation into GaAs

• US 4,385,938 A
• Filed: 09/10/1981
• Issued: 05/31/1983
• Est. Priority Date: 09/10/1981
• Status: Expired due to Fees

• Current Assignee: The United States of America As Represented By The Secretary of Agriculture
• Original Assignee: United States Of America As Represented By The Secretary Of The Air Force
• Inventors: Park, Yoon S., Yeo, Yung K.
• Primary Examiner(s): Roy, Upendra
• Application Number:
  US06/300,839
• Time in Patent Office: 628 Days
• Field of Search: 148/1.5, 148/187, 357/91, 357/61, 29/576 E, 29/576 B
• US Class Current: 438/520
• CPC Class Codes: H01L 21/2656 characterised by the implantation of both electrically active and inactive species in the same semiconductor region to be doped
• CPC Class Codes: Y10S 148/084 Ion implantation of compound devices

Abstract

p- and n- layers in GaAs by dual implants with either Ge and Ga or Ge and As into GaAs have been produced. The amphoteric behavior of Ge implants is modified in a predictable manner through control of ion dose and annealing temperature by dual implantation. The (Ge+Ga) dual implants have produced p-type conductivity for all doses up to an anneal temperature of 900° C. The (Ge+As) dual implants have yielded a significant enhancement of the n-type activity for ion doses ≧1×10¹⁵ /cm², a conductivity type conversion for intermediate doses and little effect upon p-type activity for ion doses ≦3×10¹³ /cm². By selecting appropriate ion energy, ion dose, and annealing temperature, formation of p-n junction is envisioned.

Claims

1. A method of forming a p-n junction in semiconducting GaAs device comprising:

a. dual ion implantation of Ge and Ga to provide a layer having p-type conductivity activity;

b. forming an n-layer by dual ion implantation of Ge and As at a dose in the range from about 1×

10¹⁴ /cm² extending to at least 3×

10¹⁵ /cm² at an energy level substantially less than that used to form the p-layer; and

c. annealing said device.

2. The method of claim 1, wherein the annealing temperature is approximately 900°

C. or less.

3. The method of claim 1, wherein said GaAs is Cr doped;

wherein preceding step (a) the surface is prepared by a lap and polish followed by a chemical etch;

wherein step (a) comprises an ion dose at approximately 3×

10¹³ /cm² at an energy level of approximately 400 keV; and

wherein step (b) comprises an ion dose of approximately 1×

10¹⁵ /cm² at an energy level of approximately 100 keV.

4. The method of claim 3, wherein between steps (b) and (c) the device is cleaned and then encapsulated with approximately 1000 angstroms of oxygen-free Si₃ N₄ in a pyrolytic reactor which provides rapid heating and fast deposition, the Si₃ N₄ deposition time being approximately 35 seconds at 700°

C. with the device brought to 700°

C. within 9 seconds;

wherein the annealing step (c) is done in flowing hydrogen at a temperature of 700°

C. to 1,000°

C., and during the annealing step the device rests cap-side down on a bare GaAs substrate;

wherein after the annealing step the encapsulant is stripped in 48% hydrofluoric acid; and

wherein after the annealing step an indium electrical contact is formed on the device using an ultrasonic soldering iron, following which the contact is heated at 300°

C. for three minutes in flowing argon gas to produce ohmic behavior.

5. A method of forming a layer in a semi-insulating GaAs device comprising:

a. dual ion implantation of Ge and Ga with any dose from at least as low as 1×

10¹³ /cm² up to at least 3×

10¹⁵ /cm² ; and

b. annealing, wherein an annealing temperature up to 900°

C. produces p-type conductivity activity in said layer.

6. The method of claim 5, wherein a conductivity type conversion occurs for ion doses equal or greater than 1×

10¹⁵ /cm² followed by annealing at a temperature of 900°

C. to 950°

C.; and

wherein n-type activity is produced for ion doses of approximately 1×

10¹⁵ /cm² or above followed by annealing at a temperature of approximately 950°

C. or above.

9. The method of claim 5, 6, 7 or 8, wherein between the ion implanting and annealing steps the device is cleaned and then encapsulated with approximately 1000 angstroms of oxygen-free Si₃ N₄ in a pyrolytic reactor which provides rapid heating and fast deposition, the Si₃ N₄ deposition time being approximately 35 seconds at 700°

C. with the device brought to 700°

C. within 9 seconds;

wherein the annealing step is done in flowing hydrogen at said temperature with the device resting cap-side down on a bare GaAs substrate;

wherein after the annealing step the encapsulant is stripped in 48% hydrofluoric acid.

10. The method of claim 9, wherein after the annealing step an indium electrical contact is formed on the device using an ultrasonic soldering iron, following which the contact is heated at 300°

C. for three minutes in flowing argon gas to produce ohmic behavior.

7. A method of forming a layer in a semi-insulating GaAs device comprising:

a. dual ion implantation of Ge and As at a dose in the range of approximately 1×

10¹⁴ /cm² up to at least 3×

10¹⁵ /cm² to produce n-type conductivity in said layer; and

b. annealing at a temperature in the range of at least 700°

to 1,000°

C.;

wherein a conductivity type conversion occurs for ion doses of approximately 1×

10¹⁴ /cm² ; and

wherein p-type conductivity activity results from an ion dose of approximately 3×

10¹³ /cm² or below.

8. A method of forming a layer in a semi-insulating GaAs device comprising:

a. dual ion implantation of Ge and As with a dose up to 3×

10¹³ /cm², and

b. annealing, wherein any annealing temperature in the range of 700°

to 1,000°

C. produces p-type conductivity activity in said layer.