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TV Game cartridge with expandable memory

  • US 4,386,773 A
  • Filed: 06/22/1981
  • Issued: 06/07/1983
  • Est. Priority Date: 06/22/1981
  • Status: Expired due to Fees
First Claim
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1. A memory expansion device for use in increasing ROM and adding RAM to a program cartridge without increasing or changing a number of conductor contact ribbons formed in parallel for interfacing the cartridge directly to a bus connector of an electronic video game, the cartridge comprising:

  • a first decoder to decode input codes on a plurality of address lines, output signals on a plurality of control lines an inverted enable input;

    a second decoder to decode input codes on a plurality of address lines, to output signals on a plurality of control lines, and having an inverted enable input;

    means for coupling an inverted enable input of the second decoder to one of the plurality of control lines of the first decoder;

    a first inverter coupled from one of the conductor contact ribbons providing control signals to an inverted enable input of the first decoder;

    a first AND gate having an output and a plurality of inputs, the plurality of inputs being separately coupled to the plurality of control lines of the first decoder not used to enable the second decoder and not used to enable a second ROM;

    a RAM having an inverted enable coupled to an output of the first AND gate, a R/W input, and a plurality of address inputs;

    means for coupling one of the plurality of inputs of the first AND gate to a R/W input of the RAM;

    a second ROM having an inverted enable coupled directly to a control line of the first decoder, and a plurality of address inputs;

    a pulse shaper directly coupled to a control line of the second decoder and having an output;

    a plurality of latches having a common enable coupled to the pulse shaper;

    a second AND gate having a plurality of inputs separately coupled to the control lines of the second decoder not coupled to the shaper;

    a first ROM having an inverted enable coupled to an output of the second AND gate, and a plurality of address inputs;

    a plurality of address lines each separately coupled from the conductor contact ribbons not used to provide control signals to the first inverter to the first ROM;

    means for separately coupling each of the plurality of address lines from the first ROM to the second ROM;

    means for separately coupling each of the plurality of address lines from the first ROM to the RAM;

    means for separately coupling one or more, but not all of the address lines coupled to the first ROM to the inputs of the plurality of the latches, one address line coupled to only one of the latch inputs;

    means for separately coupling the outputs of each of the plurality of latches to the second ROM address inputs;

    means to separately couple the outputs of each of the plurality of latches to the RAM address inputs;

    a plurality of data lines each separately coupled from the conductor ribbons not used to provide control signals to the first inverter, and not used to supply signals to the first and second decoder, and not used to supply address signals to the RAM, the first ROM and the second ROM, to the data inputs of the first ROM;

    means for separately coupling the plurality of data lines from the first ROM to the second ROM;

    and means for separately coupling the plurality of data lines from the second ROM to the RAM.

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