TV Game cartridge with expandable memory

• US 4,386,773 A
• Filed: 06/22/1981
• Issued: 06/07/1983
• Est. Priority Date: 06/22/1981
• Status: Expired due to Fees

• Current Assignee: Computer Magic Incorporated
• Original Assignee: Computer Magic Incorporated
• Inventors: Bronstein, John M.
• Primary Examiner(s): Hum, Vance Y.
• Application Number:
  US06/275,935
• Time in Patent Office: 715 Days
• Field of Search: 273/1 E, 273/1 GC, 273/85 G, 273/237, 273/DIG. 28, 340/723-726, 340/798, 340/799, 364/200, 364/410, 364/710, 364/900, 360/72.1, 360/74.4, 361/392, 361/395, 369/25, 369/28
• US Class Current: 463/44
• CPC Class Codes: A63F 13/95 Storage media specially adapted for storing game information, e.g. video game cartridges
• CPC Class Codes: A63F 2300/206 Game information storage, e.g. cartridges, CD ROM's, DVD's, smart cards
• CPC Class Codes: G06F 12/0623 for memory modules

Abstract

The present invention relates to a memory expansion device for use in increasing the ROM and adding RAM to a program cartridge. The program cartridge is used in association with electronic video games. The present invention relates to various electronic circuitry, including certain logic elements and ROM and RAM, allowing expansion of the memory without increasing or changing the number of conductor contact ribbons formed in parallel for interfacing the cartridge directly to the bus connector of the electronic video game.

Claims

1. A memory expansion device for use in increasing ROM and adding RAM to a program cartridge without increasing or changing a number of conductor contact ribbons formed in parallel for interfacing the cartridge directly to a bus connector of an electronic video game, the cartridge comprising:

a first decoder to decode input codes on a plurality of address lines, output signals on a plurality of control lines an inverted enable input;

a second decoder to decode input codes on a plurality of address lines, to output signals on a plurality of control lines, and having an inverted enable input;

means for coupling an inverted enable input of the second decoder to one of the plurality of control lines of the first decoder;

a first inverter coupled from one of the conductor contact ribbons providing control signals to an inverted enable input of the first decoder;

a first AND gate having an output and a plurality of inputs, the plurality of inputs being separately coupled to the plurality of control lines of the first decoder not used to enable the second decoder and not used to enable a second ROM;

a RAM having an inverted enable coupled to an output of the first AND gate, a R/W input, and a plurality of address inputs;

means for coupling one of the plurality of inputs of the first AND gate to a R/W input of the RAM;

a second ROM having an inverted enable coupled directly to a control line of the first decoder, and a plurality of address inputs;

a pulse shaper directly coupled to a control line of the second decoder and having an output;

a plurality of latches having a common enable coupled to the pulse shaper;

a second AND gate having a plurality of inputs separately coupled to the control lines of the second decoder not coupled to the shaper;

a first ROM having an inverted enable coupled to an output of the second AND gate, and a plurality of address inputs;

a plurality of address lines each separately coupled from the conductor contact ribbons not used to provide control signals to the first inverter to the first ROM;

means for separately coupling each of the plurality of address lines from the first ROM to the second ROM;

means for separately coupling each of the plurality of address lines from the first ROM to the RAM;

means for separately coupling one or more, but not all of the address lines coupled to the first ROM to the inputs of the plurality of the latches, one address line coupled to only one of the latch inputs;

means for separately coupling the outputs of each of the plurality of latches to the second ROM address inputs;

means to separately couple the outputs of each of the plurality of latches to the RAM address inputs;

a plurality of data lines each separately coupled from the conductor ribbons not used to provide control signals to the first inverter, and not used to supply signals to the first and second decoder, and not used to supply address signals to the RAM, the first ROM and the second ROM, to the data inputs of the first ROM;

means for separately coupling the plurality of data lines from the first ROM to the second ROM;

and means for separately coupling the plurality of data lines from the second ROM to the RAM.

2. The memory expansion device for use in increasing ROM and adding RAM in accordance with claim 1 wherein the smaller ranges of the address inputs on the cartridge interface comprises:

a first range of addresses, including the video game microprocessor'"'"'s reset address which enables the ROM for read operations regardless of the contents of the multi-bit latch;

a second range of addresses which enable the multi-bit latch and cause it to latch and hold the logic levels present on the cartridge interface bus lines to which the multi-bit latch inputs are connected, and the latch holds these logic levels until the latch receives a new enable input;

a third range of addresses which enable the ROM for a read operation, with the actual address presented to the ROM comprising the low order address lines of the cartridge interface bus and the output from the multi-bit latch, thus extending the addresses available for the ROM;

a fourth range of addresses which enable the RAM a read operation, with the address presented to the RAM comprising the low order address lines of the cartridge interface bus and the output from the multi-bit latch, thus extending the addresses available for the RAM; and

a fifth range of addresses which enable the RAM for a write operation, with the address presented to the RAM comprising the low order address lines of the cartridge interface bus as well as outputs from the multi-bit latch, thus extending the addresses available for the RAM as well as providing the write enable input to the RAM which is missing from the cartridge interface bus.

3. A memory expansion device for use in increasing ROM and adding RAM to a program cartridge without increasing or changing a number of conductor contact ribbons formed in parallel for interfacing the cartridge directly to a bus connector of an electronic video game, the conductor contact ribbon interfacing the cartridge to the electronic video game having no RAM write enable signal line from the video game unit to the cartridge, comprising:

a ROM containing a program and its starting address suitable for controlling a microprocessor in the video game unit, and having low order address lines, high order address lines, data lines, and an enable input;

a RAM having data lines and low order address lines connected in parallel with the equivalent lines of the cartridge interface bus and the ROM, and having high order address lines and enable inputs;

a multi-bit latch having an enable input, outputs connected to the upper order address lines of the ROM and the upper order address lines of the RAM, and having inputs connected to various input bus lines of the cartridge;

an address decoder having inputs which are connected to the upper order address lines of the cartridge, and having outputs enabled by an enable signal from the cartridge input bus, the outputs of the address decoder are each connected separately to the enable input of the ROM, to the enable inputs of the RAM, and to the enable input of the multi-bit latch, and the outputs of the address decoder are, when enabled, determined by logical combinations of the address bits presented to the inputs in such a way as to divide the range of possible address inputs to the cartridge interface into several smaller ranges;

a first pulse shaper connected between the output of the address decoder and the enable input of the multi-bit latch for rejecting logic transients occuring during the propagation of the transition of the address lines of the cartridge interface bus through the address decoder logic, thus avoiding false enables of the multi-bit latch; and

a second pulse shaper connected between the output of the address decoder and the write enable input of the RAM to reject logic transients occuring during the propagation of the transition of the address lines of the cartridge interface bus through the address decoder logic, thus avoiding false write enables of the RAM, and also to provide signal delay and pulse length limiting necessary to match the timing of the enable and period of valid data.