Low power CMOS crystal oscillator

• US 4,387,349 A
• Filed: 12/15/1980
• Issued: 06/07/1983
• Est. Priority Date: 12/15/1980
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Rapp, A. Karl
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US06/216,332
• Time in Patent Office: 904 Days
• Field of Search: 331/116 FE, 331/116 R, 368/159
• US Class Current: 331/116.0FE
• CPC Class Codes: H03B 5/04 Modifications of generator to compensate for variations in physical values, e.g. power supply, load, temperature
• CPC Class Codes: H03B 5/364 the amplifier comprising field effect transistors H03B5/366 takes precedence
• CPC Class Codes: H03K 3/3545 Stabilisation of output, e.g. using crystal

Abstract

A two transistor CMOS inverter has the two transistor gates coupled together by a coupling capacitor. D-C gate bias is supplied to each transistor through high value resistors. The P-channel transistor is biased one threshold below V_DD and the N-channel transistor is biased one threshold above ground. The biasing voltages are developed through the use of a current mirror so that the biasing is independent of processing variables and temperature. This form of biasing renders the circuit class B regardless of the source to drain voltage and ensures low current operation. A crystal oscillator created using such an inverter and biasing will operate at voltages substantially below sum of P and N thresholds and at a current level about one-fifth of that of a conventional CMOS oscillator.

Claims

1. A CMOS oscillator circuit comprising:

first and second terminals connectable to a source of operating power;

first and second complementary transistors having their source drain circuits directly connected in series across said first and second terminals;

capacitive means coupling the gates of said first and second transistors together;

resonant circuit means coupled between the drain and gate of one of said pair of transistors to create an oscillatory feedback;

a current mirror configured to develop a threshold biasing potential;

high value resistor means for coupling said threshold biasing potential to the gate of at least one of said first and second transistors; and

a buffer coupled between said current mirror and said one of said first and second transistors.