Hardware memory write lock circuit
First Claim
Patent Images
1. A memory protect system for a read/write memory having an area containing critical data which is to be protected;
- said memory having extended thereto, and being included in an overall system which has, address and data buses, and control means for accessing said memory;
comprising hardware means responsive to and for registering the occurrence of at least one predetermined access cycle in which a predetermined unlocking address appears on said address bus;
hardware means for locking said critical data memory area by preventing write operations in the absence of the prior registering of the occurrence of said at least one predetermined access cycle in which said predetermined unlocking address appears on said address bus; and
hardware means for unlocking said critical data memory area by allowing write operations only for a predetermined number of other access cycles which are subsequent to the registering of the occurrence of said at least one predetermined access cycle, each of such allowed write operations being at an address different from said predetermined address.
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Abstract
A hardware circuit for protecting against the accidental writing in an area of memory which contains critical data. In order to access the critical data memory area during a write cycle, it is necessary first to control predetermined memory access cycles which include, for example, the writing of predetermined data at a predetermined address. After detection of such a "fictitious" write cycle, the hardware allows the next write cycle to access the critical data memory area.
41 Citations
21 Claims
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1. A memory protect system for a read/write memory having an area containing critical data which is to be protected;
- said memory having extended thereto, and being included in an overall system which has, address and data buses, and control means for accessing said memory;
comprising hardware means responsive to and for registering the occurrence of at least one predetermined access cycle in which a predetermined unlocking address appears on said address bus;
hardware means for locking said critical data memory area by preventing write operations in the absence of the prior registering of the occurrence of said at least one predetermined access cycle in which said predetermined unlocking address appears on said address bus; and
hardware means for unlocking said critical data memory area by allowing write operations only for a predetermined number of other access cycles which are subsequent to the registering of the occurrence of said at least one predetermined access cycle, each of such allowed write operations being at an address different from said predetermined address. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
- said memory having extended thereto, and being included in an overall system which has, address and data buses, and control means for accessing said memory;
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12. A data processing system in which critical elements are protected against erroneous accesses comprising a plurality of elements which may be accessed by respective address signals, at least one of said elements to be protected against erroneous accesses;
- control means for accessing said elements;
hardware means responsive to and for registering the occurrence of at least one predetermined access cycle which accesses a predetermined address by predetermined address signals;
hardware means for locking said at least one element by preventing operation of said control means thereon in the absence of the prior registering of the occurrence of said at least one predetermined access cycle; and
hardware means for unlocking said at least one element by allowing an access thereto only for a predetermined number of other access cycles which are subsequent to the registering of the occurrence of said at least one predetermined access cycle, said at least one element being accessed at an address different from said predetermined address. - View Dependent Claims (13, 14, 15, 16, 17, 18, 19, 20)
- control means for accessing said elements;
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21. A data processing system in accordance with claim 21 further including means for controlling said inhibiting means to inhibit write operations in said critical elements following a disabling write access cycle to said predetermined element with different predetermined data.
Specification