Recirculating loop memory array having a shift register buffer for parallel fetching and storing

• US 4,388,701 A
• Filed: 09/30/1980
• Issued: 06/14/1983
• Est. Priority Date: 09/30/1980
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Aichelmann, Frederick J. Jr., Neves, Fernando
• Primary Examiner(s): Hecker, Stuart N.
• Application Number:
  US06/192,581
• Time in Patent Office: 987 Days
• Field of Search: 365/73, 365/77, 365/183, 365/233, 365/219, 365/221, 365/238
• US Class Current: 365/77
• CPC Class Codes: G11C 19/285 Peripheral circuits, e.g. for writing into the first stage; for reading-out of the last stage
• CPC Class Codes: G11C 19/287 Organisation of a multiplicity of shift registers

Abstract

A recirculating loop memory array is disclosed adapted for the parallel as well as serial fetching and storing of data while requiring only a single input and single output data terminal. Each loop of the array is provided with a shift register stage for parallel data accessing. A particular recirculating bit in all of the loops can be fetched in parallel into their respective shift register stages and, conversely, the bits stored in the shift register stages can be loaded in parallel into predetermined recirculating bits of their respective loops. The shift register is operated at high speed so that it may be completely loaded or unloaded during the interval between successive steppings of the loops.

Claims

1. A memory array comprising,

a plurality of recirculating loop memory elements,

said elements being clocked in synchronism so that the corresponding bits recirculate in their respective loops with the same time phase,

a shift register having a serial data input and a serial data output and comprising a number of cells equal in number to the number of said elements

a data input line coupled to said input,

a data output line coupled to said output,

first means for selectively connecting each said coil to a respective one of said elements for writing data from said cells into said elements,

second means for selectively connecting each said cell to a respective one of said elements for reading data from said elements into said cells, and

means for shifting data stored in said shift register throughout said number of cells in the time interval between successive clockings of said elements.

2. The apparatus defined in claim 1 wherein said elements are charge coupled devices.

3. The apparatus defined in claim 1 and further including third means independent of said shift register for writing data into said elements.

4. The apparatus defined in claim 3 and further including means for operating said first and third means alternatively.

5. The apparatus defined in claim 1 and further including fourth means independent of said shift register for reading data from said elements.

6. The apparatus defined in claim 5 and further including means for operating said second and fourth means alternatively.