Sample and hold circuit

• US 4,389,579 A
• Filed: 02/27/1981
• Issued: 06/21/1983
• Est. Priority Date: 02/13/1979
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Stein, Marc T.
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US06/238,729
• Time in Patent Office: 844 Days
• Field of Search: 307/353, 307/352, 307/359, 307/351, 328/151
• US Class Current: 327/96
• CPC Class Codes: G11C 27/026 associated with an amplifier G11C27/028 takes precedence
• CPC Class Codes: H03K 17/667 using complementary bipolar transistors

Abstract

A sample and hold circuit for producing an output voltage the magnitude of which is representative of the peak magnitude of a sampled input signal. The sample and hold circuit comprises a unity gain amplifier having an input terminal to receive said input signal and a cascoded output section for sourcing current at an output terminal. A discharge circuit is provided which includes a cascoded section for sinking current at said output terminal. Each of said cascoded sections being coupled to a capacitive load for charging or discharging the capacitor respectively to provide said output voltage.

Claims

1. Sample and hold circuit comprising:

charge storage means;

unity gain amplifier means having first, second inputs and an output, said output being coupled both to second input and to said charge storage means, said unit gain amplifier means being responsive to an input signal being applied to said first input for producing an output signal at said output having a magnitude substantially equal to the magnitude of said input signal such that said charge storage means is charged to the magnitude of said output signal;

discharging circuit means coupled with said unity gain amplifier means to said charge storage means for discharging said charge storage means when said magnitude of the signal developed across said charge storage means is greater than said magnitude of said input signal such that said signal developed across said charge storage means becomes substantially equal to the magnitude of said input signal; and

said unity gain amplifier means including

a. power supply conductor means adapted to be connected to a source of operating potential;

b. a differential amplifier having first and second inputs and first and second outputs, the input signal being applied to said first input, said second input being coupled to said second input of said unity gain amplifier means;

c. current mirror circuit means coupled between said first and second outputs of said differential amplifier and said power supply conductor means for providing substantially equal currents thereto in response to said input signal exceeding the magnitude of said signal appearing across said charge storage means; and

d. cascoded circuit means coupled between said second output and said second input of said differential amplifier.

2. The sample and hold circuit of claim 1 wherein said output circuit means includes:

first electron control means having first, second and control electrodes, said control electrode being coupled to said second output of said differential amplifier, said second electrode being coupled to said power supply conductor means; and

second electron control means having first, second and control electrodes, said control electrode being coupled to a bias reference means, said first electrode being coupled to said first electrode of said first electron control means, said second electrode being coupled to said output of said unity gain amplifier.

3. The sample and hold circuit of claim 2 wherein said bias reference means includes:

third electron control means having first, second, third and control electrodes, said first electrode being coupled to said control electrode of said second electron control means, said second electrode being coupled to said second output of said differential amplifier, said third electrode being coupled to said power supply conductor means; and

resistive divider means coupled between said power supply conductor means and an output terminal at which is supplied a ground reference potential, said resistor divider having first and second junction terminals which are coupled respectively to said control and first electrodes of said third electron control means such that a predetermined bias potential is produced at said control electrode of said second electron control means.

4. The sample and hold circuit of claim 1 wherein said discharging circuit means includes:

current producing means coupled to said differential amplifier having two branches for communicating currents to respective first and second loads coupled with each branch; and

circuit means coupled between said charge storage means and a ground reference potential and having an input coupled to said first load, said circuit means being responsive to the current in the first one of said branches being greater than the current in the second one of said branches for discharging said charge storage means.

5. The sample and hold circuit of claim 4 wherein each of said first and second loads comprises a current mirroring circuit having inputs coupled to each branch and a terminal connected to said ground reference potential.

6. A monolithic integrated sample and hold circuit comprising:

a unity gain amplifier having a first input terminal to which is supplied an input signal, a second input terminal and an output terminal, said output terminal being coupled both to a charge storage device and to said second input terminal such that the magnitude of the output signal appearing at said output terminal is substantially equal to the magnitude of said input signal wherein said unity gain amplifier produces current for charging the charge storage device whenever the magnitude of the input signal is greater than the magnitude of the signal appearing across the charge storage device;

discharging circuit means coupled with said unity gain amplifier to the charge storage device for discharging the charge storage device when the magnitude of the signal appearing thereacross is greater than the input signal; and

said unity gain amplifier including

a. power supply conductor means adapted to be connected to a source of operating potential;

b. a differential amplifier having first and second inputs and first and second outputs, the input signal being applied to said first input said second input being coupled to said second input terminal of said unity gain amplifier;

c. current mirror circuit means coupled between said first and second outputs of said differential amplifier and said power supply conductor means for providing substantially equal currents thereto; and

d. cascoded circuit means coupled between said second output and said second input of said differential amplifier, said output circuit means being coupled with said second input of said differential amplifier to said output of said unity gain amplifier.

7. The sample and hold circuit of claim 6 wherein said output circuit means includes:

first electron contron means having first, second and control electrodes, said control electrode being coupled to said second output of said differential amplifier, said second electrode being coupled to said power supply conductor means; and

second electron control means having first, second and control electrodes, said control electrode being coupled to a bias reference means, said first electrode being coupled to said first electrode of said first electron control means, said second electrode being coupled to said output of said unity gain amplifier.

8. The sample and hold circuit of claim 7 wherein said bias reference means includes:

third electron control means having first, second, third and control electrodes, said first electrode being coupled to said control electrode of said second electron control means, said second electrode being coupled to said second output of said differential amplifier, said third electrode being coupled to said power supply conductor means; and

resistive divider means coupled between said power supply conductor means and an output terminal at which is supplied a ground reference potential, said resistor divider having first and second junction terminals which are coupled respectively to said control and first electrodes of said third electron control means such that a predetermined bias potential is produced at said control electrode of said second electron control means.

9. The sample and hold circuit of claim 8 wherein said discharging circuit means includes:

current producing means coupled to said differential amplifier having two branches for communicating current to respective first and second loads coupled with each branch; and

circuit means coupled between said charge storage means and a ground reference potential and having an input coupled to said first load, said circuit means being responsive to the current in the first one of said branches being greater than the current in the second one of said branches for discharging said charge storage means.

10. The sample and hold circuit of claim 9 wherein each of said first and second loads comprises a current mirroring circuit having inputs coupled to each branch and a terminal connected to said ground reference potential.

11. The sample and hold circuit of claim 10 wherein said circuit means for discharging the charge storage device includes:

electron control means having first, second and control electrodes, the second electrode being coupled to said output terminal of the unity gain amplifier, said control electrode being coupled to a source of bias potential; and

additional electron control means having first, second and control electrodes, said first electrode being coupled to said terminal at which is provided a ground reference potential, said second electrode being coupled to said first electrode of said electron control means of said circuit means and said control electrode being coupled to said input of said circuit means.

12. The sample and hold circuit of claim 11 including conductor means coupled to said control electrode of said additional electron control means being adapted to receive logic control signals so that discharging of the charge storage device occurs only during a predetermined interval.