Displacement converting circuit arrangement

• US 4,389,646 A
• Filed: 03/31/1981
• Issued: 06/21/1983
• Est. Priority Date: 04/30/1980
• Status: Expired due to Term

• Current Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Original Assignee: Fuji Electric Company Limited (Fuji Electric Systems Company Limited)
• Inventors: Tago, Keiichiro
• Primary Examiner(s): Robinson, Thomas A.
• Application Number:
  US06/249,351
• Time in Patent Office: 812 Days
• Field of Search: 340/870.37, 179/78 R, 179/78 A, 179/81 R, 73/141 R, 324/60 R, 324/61 R
• US Class Current: 340/870.37
• CPC Class Codes: G01D 5/14 influencing the magnitude of a current or voltage
• CPC Class Codes: G01D 5/2417 by varying separation
• CPC Class Codes: G08C 19/10 using variable capacitance

Abstract

A displacement converting circuit arrangement comprising first and second capacitors in the form of a paired structure, at least one of the capacitors having a capacitance which is varied in response to a mechanical displacement. Means are provided for deriving first and second currents respectively proportional to the capacitances of the first and second capacitors, means for maintaining at least one of the DC currents corresponding to at least one capacitor having a variable capacitance at a fixed amount, and means for producing an output current corresponding to the difference between the DC currents, so that the output current indicates the amount of the mechanical displacement. Operation stability is improved by the simplified circuit arrangement, with consequent reduction in error and circuit failure. The movable electrode for varying the capacitance can withstand a heavy load.

Claims

1. A displacement converting circuit arrangement comprising:

first and second impedance elements, the impedance of at least one of said elements being variable in response to a mechanical displacement thereof;

means for deriving first and second DC currents, said first and second DC currents being proportional to the impedances of said first and second impedance elements, respectively;

means for deriving a current corresponding to the sum of said first and second DC currents;

a field effect transistor having said current corresponding to the sum of said first and second DC currents flowing between its source and drain electrodes, said field effect transistor maintaining said sum current at a constant value;

means for maintaining at least one of said first and second DC currents at a fixed amount;

a differential amplifier having first and second input terminals and an output terminal, said first and second DC currents being supplied to the first and second input terminals respectively of said differential amplifier; and

an output transistor coupled to the output terminal of said differential amplifier, the current at the output of said output transistor corresponding to the difference between said first and second DC currents, said output current indicating the magnitude of said mechanical displacement.

2. A displacement converting circuit arrangement as claimed in claim 1, wherein said first and second impedance elements include first and second opposed fixed electrodes and a movable electrode interposed between said fixed electrodes, said movable electrode and said first fixed electrode forming a first capacitor corresponding to said first impedance element and said movable electrode and said second fixed electrode forming a second capacitor corresponding to said second impedance element;

said displacement converting circuit arrangement further comprising

first and second diodes connected to said first and second capacitors respectively with a first polarity, a half wave of an alternating current signal being applied to said first and second capacitors through said first and second diodes to produce said first and second DC currents;

third and fourth diodes connected to said first and second capacitors respectively with a second polarity opposite to that of said first polarity, the opposite half wave of said alternating current signal being applied to said first and second capacitor through said third and fourth diodes;

first and second resistors for receiving said first and second DC currents, the voltages across said first and second resistors being coupled respectively to the first and second input terminals of said differential amplifier; and

a third resistor coupled between the source and gate electrodes of said field effect transistor, said sum current flowing through said third resistor.

3. A displacement converting circuit arrangement as claimed in claim 1, wherein a zero adjusting circuit is connected to the first and second input terminals of said differential amplifier, said output current being adjusted to a predetermined value in accordance with the impedances of said first and second impedance elements.

4. A displacement converting current arrangement as claimed in claim 3, wherein said zero adjusting circuit comprises a differential resistor having first and second ends connected to the first and second input terminals of said differential amplifier and an adjusting terminal between said first and second ends;

a second field effect transistor; and

a self-biasing resistor coupling said second field effect transistor to the adjusting terminal of said differential resistor, whereby a zero adjusting current is supplied to said second field effect transistor.

5. A displacement converting circuit arrangement as claimed in claim 1, which further comprises a load resistor coupled to the output of said output transistor, a detection resistor coupled to an input terminal of said differential amplifier and a variable feed back resistor coupled between said load and detection resistors, a part of said output current being fed back to said detection resistor through said variable feed back resistor, the resistance of said feed back resistor being adjusted to provide a predetermined output current range corresponding to that of said mechanical displacement.

6. A displacement converting circuit arrangement as claimed in claim 5, wherein the resistances of said load resistor and said detection resistor are such that the current through said variable feed back resistor is substantially zero at at least one end of said output current range.

7. A displacement converting circuit arrangement as claimed in claim 5, wherein said first and second impedance elements include first and second opposed fixed electrodes and a movable electrode interposed between said fixed electrodes, said movable electrode and said first fixed electrode forming a first capacitor corresponding to said first impedance element and said movable electrode and said second fixed electrode forming a second capacitor corresponding to said second impedance element;

said displacement converting circuit arrangement further comprising

first and second diodes connected to said first and second capacitors respectively with a first polarity, a half wave of an alternating current signal being applied to said first and second capacitors through said first and second diodes to produce said first and second DC currents;

third and fourth diodes connected to said first and second capacitors respectively with a second polarity opposite to that of said first polarity, the opposite half wave of said alternating current signal being applied to said first and second capacitors through said third and fourth diodes;

first and second resistors for receiving said first and second DC currents, said detection resistor forming part of said second resistor, the voltages across said first and second resistors being coupled to the first and second input terminals of said differential amplifier; and

a third resistor coupled between the source and gate electrodes of said field effect transistor, said sum current flowing through said third resistor.

8. A displacement converting circuit arrangement as claimed in claim 1, wherein only said second impedance element is varied in response to said mechanical displacement.

9. A displacement converting circuit arrangement as claimed in claim 8, wherein a zero adjusting circuit is connected to the first and second input terminals of said differential amplifier, said output current being adjusted to a predetermined value in accordance with the impedances of said first and second impedance elements.

10. A displacement converting circuit arrangement as claimed in claim 8, which further comprises a load resistor coupled to the output of said output transistor, a detection resistor coupled to an input terminal of said differential amplifier and a variable feed back resistor coupled between said load and detection resistors, a part of said output current being fed back to said detection resistor through said variable feed back resistor, the resistance of said feed back resistor being adjusted to provide a predetermined output current range corresponding to that of said mechanical displacement.

11. A displacement converting circuit arrangement as claimed in claim 10, wherein the resistances of said load resistor and said detection resistor are such that the current through said variable feed back resistor is substantially zero at at least one end of said output current range.

12. A displacement converting circuit arrangement as claimed in claim 8, wherein said first and second impedance elements comprise first and second fixed electrodes and said second impedance element comprises one of said fixed electrodes and a movable electrode, said fixed electrodes forming a first capacitor corresponding to said first impedance element and said one fixed electrode and said movable electrode forming a second capacitor corresponding to said second impedance element;

said displacement converting circuit arrangement further comprising

first and second diodes connected to said first and second capacitors respectively with a first polarity, a half wave of an alternating current signal being applied to said first and second capacitors through said first and second diodes to produce said first and second DC currents;

third and fourth diodes connected to said first and second capacitors respectively with a second polarity opposite to that of said first polarity, the opposite half wave of said alternating current signal being applied to said first and second capacitor through said third and fourth diodes;

first and second resistors for receiving said first and second DC currents, the voltages across said first and second resistors being coupled to the first and second input terminals of said differential amplifier; and

a third resistor coupled between the source and gate electrodes of said field effect transistor, said sum current flowing through said third resistor.

13. A displacement converting circuit arrangement as claimed in claim 9, wherein said zero adjusting circuit comprises a differential resistor having first and second ends connected to the first and second input terminals of said differential amplifier and an adjusting terminal between said first and second ends;

a second field effect transistor; and

a self-biasing resistor coupling said second field effect transistor to the adjusting terminal of said differential resistor, whereby a sum adjusting current is supplied to said second field effect transistor.

14. A displacement converting circuit arrangement as claimed in claim 10, wherein said first and second impedance elements comprise first and second fixed electrodes and said second impedance element comprises one of said fixed electrodes and a movable electrode, said fixed electrodes forming a first capacitor corresponding to said first impedance element and said one fixed electrode and said movable electrode forming a second capacitor corresponding to said second impedance element;

said displacement converting circuit arrangement further comprising

first and second diodes connected to said first and second capacitors respectively with a first polarity, a half wave of an alternating current signal being applied to said first and second capacitors through said first and second diodes to produce said first and second DC currents;

third and fourth diodes connected to said first and second capacitors respectively with a second polarity opposite to that of said first polarity, the opposite half wave of said alternating current signal being applied to said first and second capacitors through said third and fourth diodes;

first and second resistors for receiving said first and second DC currents, the voltages across said first and second resistors being coupled to the first and second input terminals of said differential amplifier; and

a third resistor coupled between the source and gate electrodes of said field effect transistor, said sum current flowing through said third resistor, a part of the output current of said differential amplifier being fed back to one of said first and second resistors through said variable resistor.