Interface adapter architecture

• US 4,390,963 A
• Filed: 09/15/1980
• Issued: 06/28/1983
• Est. Priority Date: 09/15/1980
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Puhl, Larry C., Kasley, Paul A.
• Primary Examiner(s): Ruggiero, Joseph F.
• Assistant Examiner(s): Harkcom, Gary V.
• Application Number:
  US06/187,306
• Time in Patent Office: 1,016 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 710/305
• CPC Class Codes: H04L 25/4904 using self-synchronising codes, e.g. split-phase codes

Abstract

A unique interface adapter is described which includes circuitry for recovering a clock signal and a non-return-to-zero (NRZ) data signal from a data signal transmitted on two forward data signals. The NRZ data signal is shifted into a receiving register, where address circuitry decodes the address portion of the data signal to provide a chip select signal and control circuitry decodes the control portion of the data signal to provide a register select signal, read/write signal and bus sense signal. The register select signal determines whether an output register or a data direction register is to be loaded in response to the read/write signal with the data portion of the data signal. The binary states of the data direction register determine which ones of the interface signals are to be output signals, and enable corresponding output register signals to be applied to the interface signals by way of transmission gates. While a data signal is being received on the forward data signals, the interface signals are loaded into a transmitting register and, in response to the chip select signal and clock signal, serially applied to a return data signal. The unique interface adapter may be advantageously utilized in any application where it is necessary to remotely control a plurality of interface lines with a minimum number of signal lines.

Claims

1. Interface adapter circuitry coupled to a self-clocking serial data bus having binary first and second forward data signals for receiving a binary data signal including data, address and control portions, transmitted thereon, the first and second forward data signals having a first binary state before and after the data signal, the first forward data signal having a second binary state and the second forward data signal having the first binary state for data signal bits having a binary zero state, the first forward data signal having the first binary state and the second forward data signal having the second binary state for data signal bits having a binary one state, and the first and second forward data signals having the second binary state between successive data signal bits, said interface circuitry comprising:

generating means responsive to the second binary state of the first and second forward data signals for generating a clock signal;

latch means coupled to the first and second forward data signals for storing an output signal having a binary zero state in response to the second binary state of the first forward data signal and the first binary state of the second forward data signal, and storing an output signal having a binary one state in response to the first binary state of the first forward data signal and the second binary state of the second forward data signal;

receiving register means having a plurality of output signals and being responsive to the clock signal for serially receiving the latch means output signal;

output register means having a plurality of output signals and being responsive to a first control signal for receiving the data portion of the data signal in the receiving register means;

data direction register means having a plurality of output signals and being responsive to a second control signal for receiving the data portion of the data signal in the receiving means;

interface means, having a plurality of interface signals, for applying each of the output register means output signals to a corresponding interface signal in response to a predetermined binary state of a corresponding data direction register means output signal;

detecting means responsive to the adddress portion of the data signal in the receiving register means for detecting the presence of a predetermined address signal and generating a chip select signal when the predetermined address signal is detected; and

control means responsive to the chip select signal and the control signal portion of the data signal in the receiving register means for generating the first and second control signals.

2. The interface adapter circuitry according to claim 1, wherein said serial data bus further includes a return data signal, said interface adapter circuitry being coupled to the return data signal and further including transmitting means enabled by the chip select signal to apply successive ones of the interface signals to the return data signal in response to the clock signal.

3. The interface adapter circuitry according to claim 2, wherein said transmitting means further includes transmitting register means for storing the interface signals, said transmitting register means responsive to the clock signal for storing the interface signals when the chip select signal is absent and shifting out the stored interface signals for application to the return data signal when the chip select signal is present.

4. The interface adapter circuitry according to claim 1, wherein said detecting means is further coupled to a plurality of address signal lines for determining the predetermined address signal.

5. The interface adapter circuitry according to claim 1, wherein said interface circuitry further includes complementing means responsive to a third control signal for logically complementing the latch means output signal received by the receiving register means, said control means being responsive to the control portion of the data signal in the receiving register means for providing the third control signal.

6. The interface adapter circuitry according to claims 1 or 5, wherein said control means is disabled from providing said control signals in response to detection of the first binary state of the first and second forward data signals.

7. The interface adapter circuitry according to claim 1, further including substrate means, said interface adapter circuitry formed of electrical circuit components integrated into the substrate means.

8. The interface adapter circuitry according to claim 5, wherein said complementing means further includes means responsive to the third control signal for complementing the first and second control signals.