Input/output subsystem using card reader-peripheral controller

• US 4,390,964 A
• Filed: 09/09/1980
• Issued: 06/28/1983
• Est. Priority Date: 09/09/1980
• Status: Expired due to Term

• Current Assignee: Unisys Corporation
• Original Assignee: Burroughs Incorporated (Terreno Realty Corp.)
• Inventors: Horky, Joseph F., Dockal, Ronald J.
• Primary Examiner(s): Chan; Eddie P.
• Application Number:
  US06/185,422
• Time in Patent Office: 1,022 Days
• Field of Search: 364/2MSFile,9MSFile
• US Class Current: 710/74
• CPC Class Codes: G06F 11/2221 to test input/output devices or peripheral units
• CPC Class Codes: G06F 13/124 where hardware is a sequential transfer control unit, e.g. microprocessor, peripheral processor or state-machine

Abstract

An input/output subsystem for controlling data transfer between a peripheral device, such as a card reader-peripheral unit and a main host computer. The subsystem includes: a base module which supports one or more peripheral-controllers (card reader-data link processors) which receive and process data from card readers and store them in a buffer memory for later transmittal to the host system; a Distribution control circuit which selectively connects and disconnects a data link processor to the host system; a maintenance card means for testing and checking the functioning of the data link processors.

Claims

1. In a data transfer network wherein a main host computer system receives data from a peripheral card reader mechanism via the operations of an I/O subsystem, said I/O subsystem comprising:

(a) a message level interface bus providing parallel data transfer of 16-bit words, said interface bus connecting said host computer to a base module;

(b) a base module which includes;

(b1) a common backplane connecting a card-reader data link processor to a distribution control circuit card and to a maintenance circuit card;

(b2) said distribution control circuit card for controlling the connection and disconnection of said card-reader data link processor to said main host system via said interface bus, said connection and disconnection being regulated by control signals initiated by said main host system or said card-reader data link processor;

(b3) said card-reader data link processor operating to manage the read-out of data from said card reader mechanism, said data link processor having a dedicated connection means to said card reader mechanism, said data link processor including;

(b3a) common control circuit means which include;

(i) PROM control storage means for storing individually addressable micro-code word operators;

(ii) latching register means, connected to said PROM control storage means, to store and convey an accessed word operator to a peripheral dependent circuit means for execution;

(iii) sequencing means, initiated by said main host computer, for selecting address locations to access word operators in said PROM control storage means for executing commands from said main host system;

(iv) RAM buffer memory storage means for temporary holding of data being transferred from said card reader peripheral mechanism to said main host computer, said buffer storage means including;

(iv-a) a first dedicated memory portion for storing raw data received from said card reader mechanism;

(iv-b) a second dedicated memory portion for storing translated data which has been translated and formatted by a translation means in response to said accessed micro-code word operators;

(b3b) said peripheral dependent circuit means including;

(i) logic means for executing micro-code word operators received from said common control circuit means;

(ii) means, responsive to accessed micro-code word operators from said PROM control storage means, to generate control signals for said card reader peripheral mechanism and for said sequencing means;

(iii) data multiplexor means for selecting one of multiple sources of data to be stored in said RAM buffer storage means, said sources including;

(iii-a) translated and formatted data from said translation means;

(iii-b) raw untranslated data from said card reader mechanism via said RAM buffer storage means;

(iii-c) identification coded data to identify the particular type of data link processor used;

(iii-d) result-descriptor data to inform said main host system of the completion/incompletion of each task initiated by said main host system;

(iv) address register means for supplying addresses for the read-out and the write-in of data in said RAM buffer memory storage means, said address register means receiving address data from said PROM control storage means;

(v) data latching means for temporary storing the outputs of said data multiplexor means and for transferring data to;

(v-a) said distribution control circuit card for transfer to said main host system;

(v-b) an OP-decoder for decoding micro-code word operators and effecting execution of data transfers and translation commands;

(v-c) said maintenance circuit card for testing and checking said card reader data link processor;

(v-d) said RAM buffer storage means;

(vi) said translation means being controlled by said OP-decoder for receiving untranslated raw data from said first dedicated portion of said buffer memory storage means and functioning to translate said raw data into a selected code and selected format for transfer to said second dedicated portion of said memory storage means, for subsequent transmittal to said main host system;

(vii) said OP-decoder receiving instructions from said PROM control storage means and functioning to control said translation means and to provide branching instructions to said sequencing means;

(viii) jumper encoding means connected to said data multiplexor means to provide said coded data identifying the specific card reader data link processor;

(ix) result register means, controlled by said micro-code word operators to generate said result descriptor data for transfer to said data multiplexor means;

(b4) said maintenance circuit card, which when initiated by said main host system, functions to test and check the operation of said card reader data link processor.

2. The subsystem of claim 1 wherein said translation means includes:

(a) a shift register which simultaneously receives sequences of 12 bits of card data in sections, each section representing one column of data from a data card in said card reader mechanism, said shift register providing an output to a translator-decoder means;

(b) said translator-decoder means including 16 output lines which sequentially provide a 16-bit output word having four 4-bit characters, designated ABCD, for placement in said second dedicated portion of said buffer memory;

(c) said shift register and said translator-decoder means being controlled by said micro-code sequencing means through said OP-decoder means.

3. The subsystem of claim 1 wherein said translation means includes:

(a) means to read raw card-code data which is coded in;

(i) BCL code;

or

(ii) ICT code;

or

(iii) BULL code, and to translate said raw data into EBCDIC code or Standard code.

4. The combination of claim 3 wherein said translation means includes:

means to format said EBCDIC code or Standard code into 16-bit words.

5. The subsystem of claim 1 wherein said translation means includes:

means to translate and format each four columns of 48 bits of received raw card-data, residing in said first dedicated portion of said buffer memory, into three 16-bit output words for deposit into said second dedicated portion of buffer memory for subsequent transmittal to said main host computer via parallel 16-bit word transmission.

6. The subsystem of claim 1 wherein said translation means includes:

means to translate raw data from said first dedicated portion of said buffer memory into output words of EDCBIC format, where each EDCBIC character consists of eight bits, and each two EDCBIC characters are used to form a 16-bit word of ABCD format for storage in successive locations of said second dedicated portion of said buffer memory whereby said 16-bit words may be parallel transferred to said main host computer.

7. The subsystem of claim 1 which includes:

(23a) a console peripheral-controller connected, via said base connection means, to a control console unit;

(23b) said control console unit connected to said console peripheral controller and to said maintenance circuit unit, said control console unit including;

(i) a disk memory unit for storing maintenance test routines to be used for said maintenance circuit unit in testing said common control circuit means and said peripheral dependent circuit means;

(ii) a display means for displaying the results of test routines;

(iii) a keyboard for initializing said test routines or said disk memory unit.

8. The subsystem of claim 1 wherein said translation means includes:

(24a) means to detect whether a translated character code is invalid, and

(24b) means to signal said result register means to generate coded result data for subsequent transfer to said main host system.