Method for manufacturing integrated dynamic RAM one-transistor storage cells

• US 4,391,032 A
• Filed: 07/13/1981
• Issued: 07/05/1983
• Est. Priority Date: 08/29/1980
• Status: Expired due to Fees

• Current Assignee: Siemens AG
• Original Assignee: Siemens AG
• Inventors: Schulte, Heinz
• Primary Examiner(s): Roy, Upendra
• Application Number:
  US06/282,706
• Time in Patent Office: 722 Days
• Field of Search: 148/1.5, 148/187, 29/571, 29/576 B, 29/577 C, 357/23 C, 357/23 S, 357/51, 357/91
• US Class Current: 438/251
• CPC Class Codes: H01L 28/40 Capacitors
• CPC Class Codes: H10B 12/03 Making the capacitor or connections thereto
• CPC Class Codes: H10B 12/30 DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells

Abstract

Method for manufacturing dynamic RAM one-transistor storage cells in a semiconductor chip with each cell having one integrated field effect transistor and one integrated capacitor. A semiconductor substrate surface is covered in part by a thin oxide layer and in part by a thick oxide structure. The thin oxide layer is subjected to a first ion implantation. A doped polycrystalline semiconductor material is deposited over the entire surface. The polycrystalline layer is structured by means of a photoresist mask and the underlying layers at the open places etched away to expose substrate surface. The mask is removed. A second thin oxide layer is created by oxidation over the entire surface. A second ion implantation implants ions in the second oxide layer. A second doped layer of polycrystalline material is deposited over the second layer. The second polycrystalline layer is structured by a suitable phototechnique to produce a polycrystalline structure semiconductor layer.

Claims

1. Method for manufacturing dynamic RAM one-transistor cells integrated in a semiconductor substrate, each cell consisting of one field-effect transistor and one storage capacitor, which comprises

(a) insulating areas of the semiconductor substrate for the one-transistor cells by thick oxide structures to insulate the cells from each other and covering the areas for the cells between the thick oxide structures with first thin oxide layers,

(b) forming an electrode for the storage capacitors by applying a first polycrystalline semiconductor layer over the entire surface of the thick oxide structures and the first thin oxide layers, and structuring by etching in the areas of the semiconductor substrate together with the first thin oxide layers, to leave remaining on the storage capacitor parts of the one-transistor cell areas of the semiconductor substrate a layer sequence of thin oxide as a capacitor dielectric and the polycrystalline layer as the capacitor electrode,

(c) applying a second thin oxide layer over the entire surface to form a gate oxide for the transistors,

(d) doping the transistor parts of the one-transistor cell areas of the semiconductor substrate by another ion implantation to adjust the cut-off voltage of the transistors,

(e) forming the gate electrodes of the transistors, by applying a second polycrystalline semiconductor layer over the entire surface and structuring by etching to leave parts of the second polycrystalline semiconductor on the transistor parts of the one-transistor cell areas, the combination therewith of

(f) adjusting the storage capacitors to a predetermined storage capacity after the thick oxide structures and the first thin oxide layers are formed, and using the thick oxide structures as a mask, subjecting the cell areas to an ion implantation for preparing a doped layer which with the semiconductor substrate forms a pn-junction in the storage capacitor parts in the semiconductor substrate, and

(g) performing said another ion implantation for adjusting the cut-off voltage of the transfer transistors utilizing as a mask the parts of the first polycrystalline semiconductor layer which form the electrode of the storage capacitors.

2. Method according to claim 1, wherein the ion implantation for adjusting the storage capacity is performed that first, only a doping of the first thin oxide layers takes place, and subsequently when the second thin oxide layer is applied, the doping is incorporated by diffusion from the first thin oxide layers into the storage capacitor parts of the one-transistor cell areas of the semiconductor substrate.

3. Method according to claim 1, wherein in performing the ion implantation for adjusting the storage capacity the doping is incorporated through the first thin oxide layers into the one-transistor cell areas of the semiconductor substrate, and wherein in the structuring of the first polycrystalline semiconductor layer, the layers of the semiconductor substrate containing the doping in the transistor parts of the one-transistor cell areas are removed at the same time by etching.