Cached multiprocessor system with pipeline timing

• US 4,392,200 A
• Filed: 02/27/1981
• Issued: 07/05/1983
• Est. Priority Date: 01/28/1980
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Lary, Richard F., Sullivan, Daniel T., Arulpragasam, Jega A., Giggi, Robert A.
• Primary Examiner(s): Shaw, Gareth D.
• Assistant Examiner(s): Flyntz, Terence
• Application Number:
  US06/239,129
• Time in Patent Office: 858 Days
• Field of Search: 364/200 MS File
• US Class Current: 711/140
• CPC Class Codes: G06F 12/084 with a shared cache
• CPC Class Codes: G06F 12/0846 Cache with multiple tag or data arrays being simultaneously accessible
• CPC Class Codes: G06F 12/0857 by multiple requestors
• CPC Class Codes: G06F 12/1458 by checking the subject access rights
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence
• CPC Class Codes: G06F 15/177 Initialisation or configuration control processor initialisation G06F9/4405

Abstract

A multiprocessor data processing system, the processors (30) and input/output devices (32) of which share a common control unit (CCU 10) that includes a write-through cache memory (20), a memory management circuit (22) and an address translation circuit (24). The data processing system further includes random access memory (28) and a secondary storage facility (40, 42, 68, 70). The processors (30) and the input/output devices (32) use the memory management circuit (22), the address translation circuit (24) and the cache memory (20) in an ordered pipelined sequence. When a read command "misses" the cache memory (20), the CCU accesses the memory modules (28) for allocating its cache memory (20) and for returning read data to the processors (30) or input/output devices (32). The CCU also includes a duplicate tag store (67) that maintains a copy of the cache memory address tag store (20A) thereby to enable the CCU to update its cache memory when data is written into a memory location that is to be maintained in the cache memory.

Claims

1. A data processing system that provides for the transfer of information among devices in the data processing system wherein the devices issue commands which include data signals and control information, the control information including code signals that specify the type of information transfer operation that is to be performed, device identification signals that identify the device involved in the transfer of information, and address signals that specify a location in the device to which or from which the information is to be transferred, said data processing system comprising:

A. random access memory means (28) for storing information in a plurality of addressable storage locations therein,

B. common control means (10) including

i. pipeline resource means comprising a control section (FIG. 8A) and a data section (FIG. 8B) for processing commands in an ordered pipeline sequence, said resource means comprising

a. control input means (352) in the control section for receiving control information and data input means (306) in the data section for receiving data signals,

b. associative memory means (20) that includes data store means (20B) having addressable storage locations for storing copies of information contained in said random access memory means, and address tag store means (20A) for storing memory addresses that specify the addressable storage locations in said random access memory means that are associated with the information contained in said data store means,

c. tag compare means (162) for determining whether memory data requested by a command is resident in said associative memory means,

d. queuing means (176) for receiving commands that seek to access said random access memory means, and

e. control output means (163) in the control section for transmitting control information therefrom and data output means (163) in the data section for transmitting data signals therefrom,

ii. memory interface means interconnecting the random access memory means and the common control means comprising

a. command receiving means (196) for receiving commands that read or write information in said random access memory means,

b. memory return means (65) for storing information that is read from or written into said random access memory means, and

c. memory control means (208) connected to said command receiving means and said memory return means for controlling the transfer of information among said random access memory means (184), said command receiving means, and said memory return means (65), and

iii. timing and control means (26) for controlling the operation of said common control means comprising

a. pipeline timing means for sequencing commands through successive stages of said pipeline resource means and being further responsive to said tag compare means for enabling a transfer of data requested by a command from said associative memory means to said control output means when data requested by said command is resident in the associative memory means, and

b. queuing control means (158) responsive to said tag compare means for entering a command in said queuing means (176) when data requested by said command is not resident in said associative memory means, said queuing control means being further responsive to the control information in said command for entering it in said queuing means (176) when the command seeks to write information in said random access memory means.

2. A data processing system as recited in claim 1 wherein said memory interface means includes duplicate tag store means (182) for maintaining copies of information contained in said tag store means (20A) and said timing and control means further includes:

c. updating means (336, 340,

     350) responsive to information in said duplicate tag store means (182) for updating said data store means (20B) when a command writes information in said random access memory means, and

d. allocation means (336, 340,

     350) responsive to code signals in said commands for allocating said tag store means (20A) and said data store means (20B) when information that is not resident in said associative memory means is read therefrom.

3. A data processing system as recited in claim 2 wherein said timing and control means further includes

e. means for sequencing control information of the command in a first time phase through the control section of said resource means and for sequencing the data signals of the commands in a second time phase through the data section, and

f. means (150) for monitoring the commands being sequenced through said resource means and for transmitting to said resource means data signals scheduled to update or allocate said associative memory means during a control information time slot that lacks associated data signals thereby to provide use of an otherwise vacant time slot in the data section.

4. A data processing system as recited in claim 3 wherein the pipeline resource means further includes:

a(1). memory management means (22) for controlling access to certain locations in said random access memory means, and

a(2). address translation means (24) for converting virtual addresses in the command to physical addresses in the devices of the data processing system.

5. A data processing system as recited in claim 3 further including:

C. multiprocessing means including a plurality of independently operating processor means (30) for executing instructions, and

D. processor bus means (76) for transferring information among said plurality of processing means and said common control means, said processor bus means including

i. first conductor means (102) for connection with said control input means (352) and said control output means (360) thereby to transfer control information with said common control unit, and

ii. second conductor means (104) for connection with said data input means (306) and said data output means (320) thereby to transfer data signals with said common control means.

6. A data processing system as recited in claim 5 wherein said pipeline timing means operates synchronously thereby to synchronously sequence control information through the control section (FIG. 8A) and to synchronously sequence data signals through the data section (FIG. 8A), and said timing and control means further includes:

c. processor bus timing means synchronized with said pipeline timing means for enabling a processor means to access said processor bus means (76), said processor bus timing means being operative to couple control information signals from said processor means on said first conductor means (102) thereby to enable the control information signals to be sequenced in a first time phase through the control section (FIG. 8A), and being further operative to couple data signals from said processor means on said second conductor means (104) thereby to enable the data signals to be sequenced in a delayed second time phase through the data section (FIG. 8B).

7. A data processing system as recited in claims 1, 2 or 6 wherein said common control means includes processor index means (326) in the associative memory means having

(a) an index field (325) associated with each processor means for storing address signals carried by a write command issued by said processor means, and

(b) write-in-progress indication means (327) for indicating whether said processor means seeks to write data in the random access memory means at the location specified in said index field, and

said tag compare means includes means responsive to said write-in-progress indication means for inhibiting a subsequent command from accessing the information in said data store means (20B) associated with a location in said memory means for which there is a write-in-progress, and said timing and control means further includes means for clearing said write-in-progress indication means when the write data in the data store means (20B) has been updated.

8. A data processing system as recited in claim 7 wherein each processor means includes write-in-progess flag means (79, 81, 83, 85) which when set inhibits said respective processor means from issuing a subsequent write command until its previously issued write command has updated said associative memory means.

9. A data processing system as recited in claim 7 further including

E. input/output means for providing external communication with said data processing system comprising:

i. input/output interface means (64,

     72) connected to said processor bus means (76) for externally transferring information signals with said common control means,

ii. at least one input/output device (32), and

iii. input/output bus means (60) interconnecting said input and output interface means and said input and output devices for asynchronously transferring information signal therebetween.

10. A data processing system as recited in claim 9 wherein said input/output interface means includes:

i. input/output command transmitting means (172) connected to said asynchronous bus means (60) for transmitting control information and data signals from said common control means (10),

ii. input/output command receiving means (178) connected to said asynchronous bus means (60) for receiving control information and data signals from said input/output devices, and

said timing and control means including means for controlling said command transmitting means (172) and said command receiving means (178) so that the operation of said common control means for the transfer of information is compatible with the operation of said asynchronous bus means (60) for the transfer of information.

11. A data processing system as recited in claim 9 further including:

F. secondary storage means for storing information comprising;

i. at least one secondary storage device (68) for storing information therein,

ii. controller means (40) connected to said secondary storage devices for controlling the transfer of information to and from said secondary storage devices, and

iii. mass storage bus means (46) for connection with said secondary storage controller means for transferring information signals thereover, and

iv. mass bus interface means (177) connected to said memory return means (188) and to said command receiving means (186,

     196) for transferring information between said random access memory means and said secondary storage devices over said mass storage bus means (46).

12. A data processing system as recited in claim 11 wherein said memory interface means further includes memory arbitration means (186) for determining which command will access said random access memory means.

13. A data processing system as recited in claim 12 wherein said common control means further includes:

iv. common control arbitration means (150) for receiving a plurality of commands, said arbitration means being operative to enable one of said commands to access the resources of said pipeline resources means, said arbitration means being operative to provide priority to commands from said memory return means that seek to update or allocate the associative memory means (20).