Microelectronic shadow masking process for reducing punchthrough

• US 4,394,182 A
• Filed: 10/14/1981
• Issued: 07/19/1983
• Est. Priority Date: 10/14/1981
• Status: Expired due to Term

• Current Assignee: Conexant Systems Incorporated (Synaptics Incorporated)
• Original Assignee: Rockwell International Corporation
• Inventors: Maddox, Roy L. III
• Primary Examiner(s): Roy, Upendra
• Application Number:
  US06/311,206
• Time in Patent Office: 643 Days
• Field of Search: 148/1.5, 148/187, 29/571, 29/576 B, 357/91, 357/23 S
• US Class Current: 438/163
• CPC Class Codes: H01L 2029/7863 with an LDD consisting of more than one lightly doped zone or having a non-homogeneous dopant distribution, e.g. graded LDD
• CPC Class Codes: H01L 21/0277 Electrolithographic processes
• CPC Class Codes: H01L 21/266 using masks H01L21/26586 takes precedence
• CPC Class Codes: H01L 29/42384 for thin film field effect transistors, e.g. characterised by the thickness or the shape of the insulator or the dimensions, the shape or the lay-out of the conductor
• CPC Class Codes: H01L 29/4908 for thin film semiconductor, e.g. gate of TFT
• CPC Class Codes: H01L 29/6659 with both lightly doped source and drain extensions and source and drain self-aligned to the sides of the gate, e.g. lightly doped drain [LDD] MOSFET, double diffused drain [DDD] MOSFET
• CPC Class Codes: H01L 29/6678 on sapphire substrates, e.g. SOS transistors
• CPC Class Codes: H01L 29/78621 with LDD structure or an extension or an offset region or characterised by the doping profile
• CPC Class Codes: H01L 29/78627 with a significant overlap between the lightly doped drain and the gate electrode, e.g. GOLDD
• CPC Class Codes: H01L 29/78657 SOS transistors

Abstract

A process for forming a doped region in a substrate which is in alignment with a circuit member by forming a masking member on a layer, the masking member defining the outline on the circuit member; and etching the layer employing the masking member as a mask to define the circuit member, the etching continuing such that the circuit member includes sloping side faces. Subsequently, a dopant species is implanted into the substrate so as to form the doped region, the dosage and energy of ions implanted being selected such that ions are partially blocked by the portion of the circuit member beneath the sloping side faces thereby providing a more lightly doped and more shallow distribution of implanted species region than in other regions.

Claims

1. A process for controlling the impurity profile distribution in a body of semiconductor material which includes a conductive layer, comprising the steps of:

defining a masking member on a laterally extending major surface of said body in a predetermined pattern;

etching said surface and said body through said conductive layer using said masking member as a mask so as to form a truncated, pyramidal shaped gate element having sides which slope to form tapered gate edges; and

ion implanting active regions of said semiconductor circuit using said gate element as a mask so as to form active regions having lighter and shallower degenerately doped portions under said tapered gate edges, a channel region being defined under said gate element between said active regions, the length of said channel region extending between said active regions under said gate element, the length of said channel between said degenerately doped portions being less than the length of said channel region beneath said degenerately doped portions.

2. A process as defined in claim 1, wherein said step of defining a masking member comprises the steps of:

applying a layer of photoresist to said laterally extending major surface of said body;

exposing said layer of photoresist to an electron beam and ultraviolet light in a predetermined pattern;

etching said layer of photoresist to remove the unexposed portion of said layer.

3. The process defined by claim 1, wherein conductive layer is a refractory metal polysilicon composite.

4. The process defined by claim 1 wherein said ion implantation comprises source and drain region implantation.

5. A process as defined in claim 1, wherein said body of semiconductor material includes a gate oxide layer, a polysilicon layer over said oxide layer, and a molysilicide layer over said polysilicon layer.

6. A process as defined in claim 2, wherein said photoresist is a positive photoresist.

7. A process as defined in claim 2, wherein said step of exposing said layer of photoresist comprises exposing said layer in a pattern of regions where the photoresist is to remain after subsequent processing.

8. A process as defined in claim 2, further comprising the step of subsequently exposing said layer of photoresist with ultraviolet light.

9. The process defined by claim 3, wherein said refractory metal is molysilicide.

10. A process as defined in claim 5, further comprising the step of developing said layer of photoresist and removing the unexposed portion.

11. A process for fabricating a MOS integrated circuit structure at a predetermined portion of a substrate comprising the steps of:

forming a continuous silicon layer on said substrate;

forming a continuous silicon oxide layer on said silicon layer covering at least said predetermined portion;

forming a polycrystalline silicon layer on said oxide layer such that said silicon layer is insulated from said portion;

forming a conducting layer on said polycrystalline silicon layer;

forming a resist layer over said conducting layer;

etching said resist layer to form a mask having a truncated pyramidal shape;

milling said conducting layer and said polycrystalline silicon layer using said resist layer as a mask in order to form a gate element having a shape corresponding to the truncated pyramidal shape of said resist layer mask; and

implanting dopant into said silicon layer using said gate element as a mask so that lighter and shallower degenerately doped areas are formed under the edges of said gate element.

12. The process defined by claim 11 wherein said polycrystalline silicon layer is doped with phosphorus.

13. The process defined by claim 11 wherein said silicon layer is between 4,500 and 6,000 Angstroms in thickness.

14. The process defined by claim 13 wherein said silicon oxide layer is between 100 and 350 Angstroms in thickness.

15. The process for fabricating a MOS silicon integrated circuit structure at a predetermined area on a silicon body portion comprising the steps of:

forming a continuous silicon oxide layer on said body portion covering at least one area;

forming a polycrystalline silicon layer on said oxide layer such that said silicon layer is insulated from said body portion at said area;

forming a conducting layer on said polycrystalline silicon layer;

forming a masking layer on said conducting layer;

etching said masking layer to form a masking structure having a predetermined pattern;

etching said conducting layer and said polycrystalline silicon employing said masking structure as a mask;

whereby a truncated pyramidal shaped gate element having sloping sides is formed on said oxide layer; and

ion implanting active regions of said semiconductor circuit using said gate element as a mask so as to form doped regions at opposite ends of said gate element, wherein said doped regions have lighter and shallower degenerately doped portions under said gate element sides so that during operation of said MOS silicon integrated circuit structure, carrier punch-through between said doped regions and beneath said gate element is retarded.

16. The process as defined in claim 15 wherein said conducting layer has a thickness between 3,000 and 4,000 Angstroms.

17. The process as defined in claim 16 wherein said conducting layer is composed of a N+ polysilicon first layer having a thickness between 800 and 1,200 Angstroms, and a refractory metal silicide second layer.

18. A process for controlling the impurity profile distribution in a body of semiconductor material which includes a conductive layer on a major surface thereof, comprising the steps of:

forming a masking layer over said conductive layer;

exposing said masking layer in a predetermined pattern by an electron beam;

subsequently exposing said entire masking layer to ultraviolet light;

etching said masking layer to remove the unexposed portion of said layer;

etching said surface and said body through said conductive layer using said masking member as a mask so as to form a truncated pyramidal shaped element having sloped sides; and

ion implanting active regions of said semiconductor circuit using said element as a mask so that said regions are more lightly doped and the implanted dopant distribution is more shallow directly beneath said sloped sides of said elements than in regions away from said masking member thus forming shallow active portions of said active regions at opposite ends of said element, so that a channel is defined under said element and between said active regions, and so that punch-through between said active regions and beneath said shallow active areas is retarded.

19. The process defined by claim 18, wherein conductive layer is a refractory metal-polysilicon composite.

20. The process defined by claim 18 wherein said ion implantation comprises implanting source and drain regions of a field-effect transistor.

21. A process as defined in claim 18, wherein said body of semiconductor material includes a gate oxide layer, a polysilicon layer over said oxide layer, and a refractory metalsilicide layer over said polysilicon layer.

22. A process as defined in claim 18, wherein said masking layer is a positive photoresist.

23. The process defined by claim 19, wherein said refractory metal is selected from the group consisting of molysilicide, tantalum silicide, tungsten silicide and titanium silicide.

24. A MOS process for forming source and drain regions in a substrate which includes a gate oxide layer and polysilicon layer comprising the steps of:

defining a masking member on said polysilicon layer in a predetermined pattern;

etching said polysilicon layer to form a gate employing said masking member as a mask, said etching forming a truncated pyramidal gate structure having sloped edge faces, the base of said pyramidal gate structure being disposed on said gate oxide layer;

ion implanting said substrate to form said source and drain regions through said gate oxide, the dosage and energy of ions implanted being selected so that a lower concentration and more shallow distribution of impurities is implanted in substrate regions beneath said sloped edge faces than in substrate regions not protected by said gate structures so that a channel is defined beneath said gate and between said source and drain regions, and so that the length of said channel is shorter near said gate and longer away from said gate; and

whereby during subsequent processing steps, said lower concentration of impurities does not substantially diffuse, thereby providing more precise alignment between said gate structure and said source and drain regions.

25. A process for forming a MOS field effect transistor on a substrate comprising the steps of:

forming a gate oxide layer on said substrate;

forming a layer of polysilicon over said gate oxide layer;

defining a masking member on said polysilicon layer in a predetermined shape including sloping side faces;

etching said polysilicon layer employing said masking member as a mask to form a gate for said field-effect transistor, including etching said polysilicon layer under said masking member to form said gate with sloping side faces which extend from the sloping side faces of said masking member;

ion implanting said substrate to form source and drain regions by ion implanting through said gate oxide, such that some implantation occurs in the substrate region beneath said sloping side faces of said gate, thereby forming more lightly doped source and drain regions beneath said side faces and more heavily doped source and drain regions in substrate areas unprotected by said masking member so that punch-through between said source and drain regions deep within said substrate is retarded during operation of said field effect transistor; and

whereby during subsequent processing steps, the lower concentration of impurities in said more lightly doped source and drain regions does not substantially diffuse beneath said gate, thereby providing more precise alignment between said gate and said source and drain regions.

26. In a process for forming a doped region in a substrate which is in alignment with a circuit member, the improved steps comprising:

forming a masking member on a layer, said masking member defining the outline of said circuit member;

etching said layer employing said masking member as a mask to define said circuit member, said etching continuing such that said circuit member includes sloping side faces;

implanting impurity ions into said substrate so as to form said doped region, the dosage and energy of ions implanted being selected such that ions are blocked by said circuit member with a portion of said impurity dosage allowed to pass through said sloping side faces thereby producing said doped region with a more lightly doped and more shallow distribution of implanted impurity beneath said sloping side faces so that punch-through deep within said substrate is retarded; and

whereby in subsequent processing steps said more lightly doped regions do not substantially diffuse beneath said circuit member.