Alignment-enhancing feed-through conductors for stackable silicon-on-sapphire wafers

• US 4,394,712 A
• Filed: 03/18/1981
• Issued: 07/19/1983
• Est. Priority Date: 03/18/1981
• Status: Expired due to Term

• Current Assignee: Intersil Corporation (Renesas Electronics Corporation)
• Original Assignee: General Electric Company
• Inventors: Anthony, Thomas R.
• Primary Examiner(s): Kucia, R. R.
• Application Number:
  US06/244,854
• Time in Patent Office: 853 Days
• Field of Search: 174/68.5, 361/412, 361/411, 361/395
• US Class Current: 361/779
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 2225/06541 Conductive via connections through the device, e.g. vertical interconnects, through silicon via [TSV] manufacturing via connections per se H01L21/76898
• CPC Class Codes: H01L 23/5385 Assembly of a plurality of insulating substrates
• CPC Class Codes: H01L 25/0657 Stacked arrangements of devices
• CPC Class Codes: H01L 25/50 Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00 H01L21/50 takes precedence
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H05K 1/0306 Inorganic insulating substrates, e.g. ceramic, glass
• CPC Class Codes: H05K 2201/096 Vertically aligned vias, holes or stacked vias
• CPC Class Codes: H05K 2201/10666 Plated through-hole for surface mounting on PCB
• CPC Class Codes: H05K 2203/0455 PTH for surface mount device [SMD], e.g. wherein solder flows through the PTH during mounting
• CPC Class Codes: H05K 3/3436 having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: H05K 3/368 parallel to each other H05K3/361 takes precedence
• CPC Class Codes: Y02P 70/50 Manufacturing or production processes characterised by the final manufactured product

Abstract

Alignment-enhancing electrically conductive feed-through paths are provided for the high-speed low-loss transfer of electrical signals between integrated circuits of a plurality of silicon-on-sapphire bodies arrayed in a stack. The alignment-enhancing feed-throughs are made by a process involving the drilling of holes through the body, double-sided sputtering, electroplating, and the filling of the holes with solder by capillary action. The alignment-enhancing feed-throughs are activated by forming a stack of wafers and remelting the solder whereupon the wafers, and the feed-through paths, are pulled into alignment by surface tension forces.

Claims

1. An article of manufacture comprising in combination:

(a) a plurality of bodies, said bodies being disposed in an array, each said body being adjacent to a next body with a relatively uniform gap therebetween, each said body having top and bottom major opposed surfaces substantially parallel to each other and an outer peripheral edge area interconnecting said major surfaces, said array having an array axis, said array axis being substantially perpendicular to the major surfaces of each body of said array; and

(b) means for electrically interconnecting said bodies, said means

(i) having a substantially circular cross section,

(ii) having a plurality of materials of construction, said materials being arranged about said cross section in the region between said top and bottom surfaces as a first core material, a second material circularly encompassing said core material and a third outermost material circularly encompassing said first and second materials, the material of said cross section in said gap being substantially said first core material;

(iii) extending through and between each said body in said array,

(iv) having a means axis, said means axis being substantially parallel to said array axis, and

(v) being arranged in a substantially periodic means array, said means array having a means axis-to-means axis spacing substantially equal to twice the diameter of said cross section.

2. The article of claim 1 wherein each said body is composed of a single material, said single material being one selected from the group consisting of silicon, germanium, gallium arsenide, gallium phosphide, indium antimonide, cadmium telluride and zinc sulfide.

3. The article of claim 1 wherein each said body is a composite, each said body having a single crystal sapphire substrate and a contiguous overlaying epitaxially-grown layer of single crystal silicon, said top major surface being the exposed surface of said silicon layer, said bottom major surface being the exposed surface of said sapphire substrate and said outer peripheral edge area encompassing both said sapphire substrate and said layer of silicon.

4. The article of claim 1 wherein said body is composed of an insulating material, said insulating material being one selected from the group consisting of alumina, quartz, glass, and beryllium oxide.

5. The article of claim 1 wherein said first core material is a lead-tin alloy, said second material is copper, and said third outermost material is gold.

6. The article of claim 1 wherein said first core material is a lead-tin alloy, said second material is copper, and said third outermost material is nichrome.

7. The article of claim 1 wherein said gap is less than or equal to the circumference of said circular cross section.

8. The article of claim 1 wherein said gap is less than or equal to the relief height plus the circumference of said circular cross section.