Pulse-code modulation signal processing circuit

• US 4,394,762 A
• Filed: 01/06/1981
• Issued: 07/19/1983
• Est. Priority Date: 01/06/1981
• Status: Expired due to Fees

• Current Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Original Assignee: Tokyo Shibaura Denki Kabushiki Kaisha
• Inventors: Nabeshima, Daiki
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US06/222,769
• Time in Patent Office: 924 Days
• Field of Search: 371/38, 371/37, 360/32, 360/38, 360/53
• US Class Current: 714/758
• CPC Class Codes: G11B 20/1809 by interleaving
• CPC Class Codes: G11B 20/1876 Interpolating methods

Abstract

A PCM signal processing circuit records a predetermined number of PCM signals and also parity signals and a CRC signal after conversion into a signal having a data format conforming to the television signal with a VTR and detects the PCM signals from the reproduced signal from the VTR. In this PCM signal processing circuit, when the preset bit number of the PCM signals is greater than a reference bit number, the number of parity signals is reduced, and extra bit portions of the individual PCM signals are allotted to the vacant parity signal slot obtained as a result of the reduction of the parity signal number.

Claims

1. A signal processing circuit for recording PCM signals, comprising:

A/D coverting means for sampling at a predetermined frequency analog signals to be recorded and converting sampled signals into digital signals forming sample words;

mode determining means for generating a first mode signal when a sample word from the A/D converting means consists of N bits, where N is a positive integer, and a second mode signal when a sample word from the A/D converting means consists of N+M bits, where M is a positive integer;

error correction word generating means connected to said A/D converting means and mode determining means for generating, in response to a first mode signal, K+L error correction words, each consisting of N bits, and where K and L are positive integers, for a predetermined number of N-bit sample words and for generating, in response to a second mode signal, K error correction words each consisting of M+N bits for the same number of (M+N)-bit words as that of the N-bit sample words;

first memory means connected to said A/D converting means and said error correction word generating means for interleaving error correction words among the sample words corresponding thereto;

arranging means to desired PCM signals connected to said first memory means and mode determining means for allotting, in response to a first mode signal, first by said predetermined number of N-bit sample words and then secondly the K+L error correction words to one horizontal scanning segment of a television signal and for dividing, in response to a second mode signal, each of the sample words and error correction words into an M-bit component and an N-bit component and then allotting to the horizontal scanning segment the M-bit components of said predetermined number of sample words, the M-bit components of K error correction words, the N-bit components of said predetermined number of sample words, and the N-bit components of K error correction words in that order, thereby allotting N-bit components of said predetermined number of said sample words and the N-bit components of K error correction words to a slot to which L error correction words are allotted in response to a first mode signal; and

means for recording on a video tape the PCM output signals from said arranging means and mode determining means in a form which is adapted to a data format for the television signal.

2. A signal processing circuit according to claim 1 wherein said first memory means outputs an (M+N)-bit parallel signal, and said arranging means has a shift register of the series-in/parallel-out type connected to receive N-bit components from said first memory means and a gate having two input terminals connected respectively to the M-bit output of said first memory means and the output of the shift register, and a control terminal connected to said mode determining means, said gate allowing the passage of the output signal from said first memory means in response to a first mode signal and allowing first the passage of the output signal from said first memory means and then the passage of the output signal from the shift register in response to a second mode signal.

3. A signal processing circuit according to claim 1 wherein said error correction words generating means includes a first generator connected to the output terminal of said sample word generating means for producing a first group of parity words on the basis of the predetermined number of words, and a second generator connected to the output terminal of said word generating means and said mode determining means for producing a second group of parity words on the basis of the predetermined number of sample words in accordance with a second mode.

4. A signal processing circuit according to claim 1, wherein said recording means further includes a third generator connected to said arranging means for producing a cyclic redundancy check signal by processing the output signal from said arranging means in each horizontal scanning segment in the television signal with an operand.

5. A signal processing circuit according to claim 1, further comprising:

reproducing means to reproduce the recorded PCM output signals having detecting means for detecting sample words and error correction words from one horizontal scanning segment of a signal reproduced from the video tape;

second memory means for deinterleaving the sample words and error correction words output from said detecting means;

error correcting means for error-correcting the words output from said second memory means;

D/A converting means for converting the digital output signals from said error correcting means into analog signals.

6. A signal processing circuit according to claim 5 wherein said first memory means outputs an (M+N)-bit parallel signal, and said arranging means has a shift register of the series-in/parallel-out type connected to receive N-bit components from said first memory means and a gate having two input terminals connected respectively to the M-bit output of said first memory means and the output of the shift register, and a control terminal connected to said mode determining means, said gate allowing the passage of the output signal from said first memory means in response to a first mode signal and allowing first the passage of the output signal from said first memory means and then the passage of the output signal from the shift register in response to a second mode signal.

7. A signal processing circuit for recording PCM signals, comprising:

A/D converting means for sampling at a predetermined frequency analog signals to be recorded and converting sampled signals into a digital signal forming sample words;

mode determining means for generating a first mode signal when a word from the A/D converting means consists of N bits, where N is a positive integer, and a second mode signal when a word from the A/D converting means consists of N+M bits, where M is a positive integer;

error correction word generating means connected to said A/D converting means and mode determining means for generating, in response to a first mode signal, K+L error correction words, each consisting of N bits, and where K and L are positive integers, for a predetermined number of N-bit sample words and for generating, in response to a second mode signal, K error correction words each consisting of M+N bits for the same number of (M+L)-bit words as that of the N-bit words;

arranging means connected to said A/D converting means and said error correction word generating means for allotting, in response to a first mode signal, first by said predetermined number of N-bit sample words and secondly K+L error correction words to one horizontal scanning segment of a television signal and for dividing, in response to a second mode signal, each of the sample words and error correction words into an M-bit component and an N-bit component and then allotting to the horizontal scanning segment the M-bit components of said predetermined number of sample words, the M-bit components of K error correction words, the N-bit components of said predetermined number of sample words and the N-bit components of K error correction words in that order, thereby allotting the N-bit components of said predetermined number of sample words and the N-bit components of K error correction words to a slot to which L error correction words are allotted in response to a first mode signal;

first memory means for interleaving each word in the horizontal scanning segment output from said arranging means; and

means for recording on a video tape the PCM output signals from said first memory means and mode determining means in a form which is adapted to a data format for the television signal.

8. A signal processing circuit according to claim 7 further comprising:

reproducing means to reproduce the recorded PCM output signals;

second memory means for deinterleaving the PCM signals reproduced from the video tape;

detecting means for detecting sample words and error correction words from one horizontal scanning segment of an output signal from said second memory means;

error correcting means for error-correcting the sample words output from said second memory means; and

D/A converting means for converting the digital output signals from said error correcting means to analog signals.

9. A signal processing circuit according to claim 7 wherein said error correction words generating means includes a first generator connected to the output terminal of said sample word generating means for producing a first group of parity words on the basis of the predetermined number of sample words, and a second generator connected to the output terminal of said sample word generating means and said mode determining means for producing a second group of parity words on the basis of the predetermined number of words in accordance with a second mode.

10. A signal processing circuit according to claim 7 wherein said recording means further includes a third generator connected to said first memory means for producing a cyclic redundancy check signal by processing the output signal from said first memory means in each horizontal scanning segment in the television signal with an operand.