Error-correcting system

• US 4,394,763 A
• Filed: 04/24/1981
• Issued: 07/19/1983
• Est. Priority Date: 08/31/1979
• Status: Expired due to Term

• Current Assignee: Fujitsu Limited
• Original Assignee: Fujitsu Limited
• Inventors: Takahashi, Masao, Nagano, Genzo
• Primary Examiner(s): ATKINSON, CHARLES
• Application Number:
  US06/261,181
• Time in Patent Office: 816 Days
• Field of Search: 371/38, 371/13, 371/10, 364/200, 364/900
• US Class Current: 714/6.1
• CPC Class Codes: G06F 11/1024 Identification of the type of error
• CPC Class Codes: G11C 29/70 Masking faults in memories by using spares or by reconfiguring

Abstract

An error-correcting system is disclosed, which is located between a main memory and a central processing unit. The system includes a relief bit memory, an ECC or Error Correction Code logic circuit, a switching circuit and a correction controlling circuit. The ECC logic circuit detects the occurrence of a soft error and a hard error. When a hard error occurs in the memory, the defective memory cell thereof is switched to the relief bit memory. Accordingly, data to be written into the main memory or the relief bit memory is switched by means of the switching circuit. Similarly, data to be read from the main memory or the relief bit memory is also switched by the switching circuit. The data to be stored in the relief bit memory is validated by means of the ECC logic circuit and the switching circuit. Further, the (n+1)-bit soft and hard errors are reduced to n-bit soft and hard errors by means of the ECC logic circuit and the switching circuit.

Claims

1. An error-correcting system, operatively connected between a main memory and a central processing unit, comprising:

an error correction code logic circuit, which can correct n-bit errors, where n is a positive integer, and detect n+1-bit errors;

first means, operatively connected to said central processing unit and said error correction code logic circuit, for discriminating whether an error, occurring in said main memory, is a soft error or a hard error;

second means for storing data for a defective memory cell of said main memory, which defective memory cell produces the hard error;

third means, operatively connected to said main memory, said first means and said second means, for, when a hard error is found by using said first means, switching the data for the defective memory cell of said main memory to said second means; and

fourth means, operatively connected to said first means and said third means, for effecting a validation operation with respect to the data to be stored in said second means.

2. An error-correcting system as set forth in claim 1, wherein said error-correcting system further comprises fifth means, operatively connected to said fourth means and said error correction code logic circuit, for, when n+1-bit errors are found during said validation operation, reducing the n+1-bit errors to n-bit errors through said error correction code logic circuit.

3. An error-correcting system as set forth in claim 1, wherein said first means comprises:

means for producing corrected data for a soft or hard error by means of said error correction code logic circuit;

means for writing the corrected data into the memory cell in which a soft or hard error occurs; and

means for reading the written corrected data from the memory cell, and if the error correction code logic circuit determines that the corrected data still includes an error, said first means discriminates the occurrence of the hard error and if the error correction code logic circuit determines that the corrected data includes no error, the first means discriminates the occurrence of the soft error.

4. An error-correcting system as set forth in claim 1, wherein said second means comprises of one or more relief bit memories which can relieve the defective memory cells of said main memory.

5. An error-correcting system as set forth in claim 4,

wherein said main memory comprises k words, where k is an integer, and

wherein the k words comprising said main memory are divided into a plurality of groups, and each of said relief bit memories are allotted to one of these groups, respectively, each of the relief bit memories comprising 1 bit in width and k bits in length.

6. An error-correcting system as set forth in claim 1,

wherein said error correction code logic circuit produces write data and an error-position indicating signal,

wherein said main memory produces read data, and

wherein said third means comprises a switching circuit comprising first and second switching gates each having first and second inputs, said second switching gates further having third inputs, both said first and second switching gates arranged in a bit-to-bit fashion, each of the first switching gates receives, at its first input, the write data from the error correction code logic circuit, and at its second input, the error-position indicating signal produced by the error correction code logic circuit, and one of the first switching gates, specified by the error-position indicating signal, transfers the write data to said second means, and each of said second switching gates receives, at its first input, the read data from the main memory, at its second input, the data stored in said second means, and at its third input, said error-position indicating signal, and one of the second switching gates, specified by the error-position indicating signal transfers the read data to the error correction code logic circuit.

7. An error-correcting system as set forth in claim 1, wherein said fourth means comprises a correction controlling circuit cooperating with said error correction code logic circuit and controling said third means, said fourth means functioning to store corrected data, corresponding to the hard error, in said second means.

8. An error-correcting system as set forth in claim 2, wherein said fifth means produces a first logic and a second logic sequentially at the output of said second means, until the n+1-bit errors are reduced to n-bit errors through said error correction code logic circuit.

9. An error-correcting system as set forth in claim 8, wherein said first and second logics are externally supplied to the output of said second means.

10. An error-correcting system as set forth in claim 8,

wherein said fifth means comprises an exclusive OR gate, and

wherein said first and second logics are produced by the output data from said second means or by the inverted output data from said second means, by means of said exclusive OR gate.

11. An error-correcting system, operatively connected between a main memory and a central processor, comprising:

a relief memory;

a switching circuit, operatively connected to said main memory and said relief memory, for switching between said main memory and said relief memory and for passing data therethrough;

an error correction code logic circuit, operatively connected to said central processor and said switching circuit, for detecting hard and soft errors, for generating an error detection signal and an error position signal in dependence upon the data output by said switching circuit and for outputting corrected data; and

a correction controlling circuit, operatively connected to said switching circuit and said error correction code logic circuit, for generating a relief switching signal and a control signal in dependence upon the error detection signal and the error position signal;

said switching circuit switching to said relief memory, when the hard error is detected and storing the corrected data in said relief memory when the hard error is detected and storing the corrected data in the main memory when the soft area is detected, in dependence upon the relief switching signal and the control signal.