Precision digital random data generator

• US 4,395,703 A
• Filed: 06/29/1981
• Issued: 07/26/1983
• Est. Priority Date: 06/29/1981
• Status: Expired due to Fees

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Piosenka, Gerald V.
• Primary Examiner(s): Miller, C. D.
• Application Number:
  US06/278,261
• Time in Patent Office: 757 Days
• Field of Search: 340/347 CC, 340/347 AD, 331/78, 364/717, 375/34, 328/14, 328/158
• US Class Current: 341/899
• CPC Class Codes: G06F 7/588 Random number generators, i.e. based on natural stochastic processes
• CPC Class Codes: H03K 3/84 Generating pulses having a predetermined statistical distribution of a parameter, e.g. random pulse generators

Abstract

A precision digital random data generator comprising a matched pair of D-type flip-flops, a differential amplifier for comparing integrated outputs of the flip-flops, provisions for a noisy analog input of the general type (n)t feeding one input of the comparator with the output of the comparator feeding a D input of one of the D type flip-flops which generates an output which statistically correlates with the analog input and is also fed to the other input of the comparator.

Claims

1. An electronic circuit for amplifying and synchronizing a random analog input noise signal having a statistical characteristic to produce a useful random data digital signal, the digital signal having statistical characteristics essentially the same as the characteristics of the random analog signal, the circuit comprising:

a system clock signal input;

first integrator means connected to said input for generating a first integrated signal from a system clock signal applied to said input;

a second integrator means connected to said input for generating a second integrated signal utilizing the system clock signal and for generating the random data digital signal at an output thereof;

both integrator means being clocked at the same rate;

means for comparing said first and second integrated signals and for generating an output of said comparing means responsive to said comparison, said output of said comparing means being a second input of said second bias means; and

means for applying a time varying noise signal in superposition with said first integrated signal.

2. The electronic circuit according to claim 1 wherein at least one of said first and second integrator means further comprises:

a low pass filter.

3. The electronic circuit according to claim 2 wherein at least one of said first and second integrator means further comprises:

a flip-flop.

4. The electronic circuit according to claim 1, 2 or 3 wherein at least an active portion of each of said first and second integrator means comprises a single monolithic circuit and wherein said active portions are on a single monolithic semiconductor chip.