Low power CMOS frequency divider

• US 4,395,774 A
• Filed: 01/12/1981
• Issued: 07/26/1983
• Est. Priority Date: 01/12/1981
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Rapp, Adolph K.
• Primary Examiner(s): Heyman, John S.
• Assistant Examiner(s): Hudspeth, David R.
• Application Number:
  US06/224,591
• Time in Patent Office: 925 Days
• Field of Search: 307/220 C, 307/221 C, 307/223 C, 307/225 C, 307/452, 307/481, 307/576, 307/579, 307/583, 307/585, 307/269, 307/271, 368/157, 368/159, 368/219, 377/114, 377/121, 377/122
• US Class Current: 377/114
• CPC Class Codes: H03K 19/0963 using transistors of complementary type H03K19/0966 takes precedence
• CPC Class Codes: H03K 23/44 using field-effect transistors H03K23/46 and H03K23/425 take precedence

Abstract

Means are described for generating a pair of oscillator signals that will respectively drive P and N channel transistors in Class B. These signals are used to clock a synchronous inverter stage that will only change state during the appropriate time interval. Pairs of such stages are cascaded using common clocking to create a shift register which drives an output inverter, the output of which is coupled back to the input of the register. The output stage also has series-coupled P and N-channel transistor pairs for each pair of clocked inverters. Each transistor pair has its gates driven by the respective pair of clocked inverters. The output stage switches at a frequency which is a submultiple of the oscillator frequency, with the submultiple being equal to the number of inverters minus one. Since the inverters are fully Class B there is no direct current conduction due to simultaneous transistor conduction. The clock input capacitance of the shift register becomes part of the oscillator turning capacitance and thus requires no power dissipation. Furthermore, since the inverters switch at a submultiple of the oscillator frequency, output capacitance charging and discharging power is made negligible.

Claims

1. A CMOS frequency divider comprising:

an even number (K) greater than two of cascaded inverters, each one comprising first and second P channel transistors, third and fourth N channel transistors, means for coupling the source-drain circuits of said P and N channel transistors in series across first and second power supply rails connectable to a source of operating power, means for coupling the gates of said second and third transistors to an inverter input terminal, means for coupling the drain electrodes of said second and third transistors to an inverter output terminal and clock means for alternately switching said first and fourth transistors between conductive and nonconductive states;

means for bypassing one of said first and fourth transistors in at least one of said inverters by connecting the respective drain to the respective source of said one transistor;

a combining clocked inverter having K/2 inputs coupled respectively to alternate outputs of said cascaded clocked inverters and an output coupled to the input of the first of said cascaded clocked inverters, said combining clocked inverter comprising;

K/2 plus one P channel transistors and K/2 plus one N channel transistors, having their source-drain circuits coupled in series between said power supply rails;

means for coupling the gate electrodes of the P and N channel transistors that have their sources coupled directly respectively to said first and second power supply rails to said clock means for alternately switching said first and fourth transistors; and

means for coupling each of the gates of the remainder of said P channel transistors to a corresponding one of the remainder of said N channel transistor gates, to provide said K/2 inputs.

2. The frequency divider of claim 1, further comprising:

K/2 minus one additional P channel transistors having their source electrodes coupled to the positive of said power supply rails, their respective gate electrodes coupled to the gate electrodes of said N channel transistors that comprise the input terminals of said combining clocked inverter except for that N channel transistor having its drain coupled directly to said combining clocked inverter output, and their drain electrodes coupled to the respective drain electrodes of said N channel transistor drain electrodes; and

K/2 minus one additional N channel transistors, having their source electrodes coupled to the negative of said power supply rails, their respective gate electrodes coupled to the gate electrodes of said P channel transistors that comprise the input terminals of said combining clocked inverter except for that P channel transistor having its drain coupled directly to said combining clocked inverter output, and their drain electrodes coupled to the respective drain electrodes of said P channel transistors.