Stuff synchronization device with reduced sampling jitter

• US 4,397,017 A
• Filed: 03/02/1981
• Issued: 08/02/1983
• Est. Priority Date: 03/02/1981
• Status: Expired due to Term

• Current Assignee: Nippon Electric Company Limited (NEC Corporation)
• Original Assignee: Nippon Electric Company Limited (NEC Corporation)
• Inventors: Rokugo, Yoshinori
• Primary Examiner(s): Olms, Douglas W.
• Application Number:
  US06/239,865
• Time in Patent Office: 883 Days
• Field of Search: 370/102, 370/84, 340/347 DD, 375/106
• US Class Current: 370/506
• CPC Class Codes: H04J 3/073 Bit stuffing, e.g. PDH

Abstract

It has now been confirmed as regards a stuff (justification) synchronization device for each of plesiochronous input pulse sequence to be time division multiplexed that a low frequency jitter component appears in a synchronous output pulse sequence from the effect of sampling phase lags of read pulse sequences for reading the output pulse sequence for stuffing from an elastic memory (36) of the device relative to write pulse sequences for storing the input pulse sequence in the memory at a sampling interval equal to the memory capacity. The jitter is reduced (1) by selecting a prime number, preferably thirteen and more preferably seventeen or nineteen, as the memory capacity, (2) by cyclically using selected write and read pulse sequences for phase lag monitoring, or (3) by rendering the sampling interval either random or equivalently random.

Claims

1. A pulse stuff synchronization device responsive to an input pulse sequence comprising input information pulses at an input bit rate for producing an output pulse sequence comprising output information pulses and stuff pulses in selected ones of consecutive pulse slots defined by a reference clock pulse sequence of an output bit rate higher than said input bit rate, said consecutive pulse slots being divisible into a succession of frames and including that at least one predetermined pulse slot in each frame in which said output pulse sequence includes a selected one of said output information pulses and said stuff pulses to arrange said input information pulses in said output pulse sequence as the respective output information pulses in synchronism with said reference clock pulse sequence, said device comprising (a) i one-bit memory cells, where i represents a predetermined natural number equal at least to two, (b) means for producing first through i-th write pulse sequences having first through i-th cyclically retarding write pulse phases, respectively, for use in storing said input information pulses cyclically in said memory cells, (c) gapping means responsive to said reference clock pulse sequence and a control pulse produced in one frame for providing a gap between the reference clock pulses at the predetermined pulse slot in a frame next succeeding said one frame to produce a gapped clock pulse sequence in response to successive control pulses, (d) means responsive to said gapped clock pulse sequence for distributing the gapped clock pulses into first through i-th read pulse sequences having first through i-th cyclically retarding read pulse phases, respectively, to produce said first through said i-th read pulse sequences, said first read pulse phase having a phase lag relative to said first write pulse phase, (e) means responsive to said first through said i-th read pulse sequences for cyclically reading as said output information pulses the input information pulses stored in said memory cells, (f) means for sampling phase lags of said first through said i-th read pulse phases relative to said first through said i-th write pulse phases, respectively, to provide sampled phase lags from time to time, (g) phase lag monitoring means coupled to said sampling means for monitoring said sampled phase lags to successively produce stuff demand pulses every time said sampled phase lags decrease below a predetermined threshold and (h) supplying means for supplying said stuff demand pulses as said successive control pulses to said gapping means, said output pulse sequence being subject to a jitter component when said sampled phase lags are sampled at a sampling interval substantially equal to i input bit periods, wherein the improvement comprises jitter reducing means for reducing said jitter component, said jitter reducing means comprising:

a random pulse generator responsive to said reference clock pulse sequence for producing a sequence of random pulses having a pulse interval variable at random between i and (i-k) output bit periods, both inclusive, where k represents an integer preselected from natural numbers less than said predetermined natural number; and

means coupled to a selected one of said sampling means and said phase lag monitoring means and responsive to said random pulse sequence for randomizing time intervals between said sampled phase lags.

2. A pulse stuff synchronization device as claimed in claim 1, wherein:

said write pulse sequence producing means is resettable and produces said first write pulse sequence when reset;

said gapped clock pulse distributing means being resettable and producing said first read pulse sequence when reset;

said randomizing means comprising;

means coupled to said resettable write pulse sequence producing means and said resettable gapped clock pulse distributing means and responsive to each of said random pulses for concurrently resetting said resettable write pulse sequence producing means and said resettable gapped clock pulse distributing means to make said resettable write pulse sequence producing means produce, before the concurrent reset, the write pulse sequences, equal in number to the at least one input bit period of the pulse interval next preceding said each random pulse except for the next previously produced first write pulse sequence, and to make said resettable gapped clock pulse distributing means produce, before the concurrent reset, the read pulse sequence, equal in number to the at least one output bit period of the pulse interval next preceding said each random pulse except for the next previously produced first read pulse sequence; and

means for supplying said first write and read pulse sequences to said sampling means;

said sampling means repeatedly using as said sampled phase lags the phase lag of said first read pulse phase relative to said first write pulse phase.

3. A pulse stuff synchronization device as claimed in claim 1, wherein:

said randomizing means comprises;

means coupled to said write pulse sequence producing means and said gapped clock pulse distributing means and responsive to each of said random pulses for concurrently selecting one of said write pulse sequences and one of said read pulse sequences, said selected write pulse sequence having a random write pulse phase lagging in the cyclic order of said first through said i-th write pulse sequences behind said first write pulse phase by at least one input bit period corresponding to the at least one output bit period of the pulse interval next preceding said each random pulse, said selected read pulse sequence having a random read pulse phase lagging in the cyclic order of said first through said i-th read pulse sequences behind said first read pulse phase by the at least one output bit period of the pulse interval next preceding said each random pulse; and

means for supplying said sampling means with the selected write and read pulse sequences successively selected in response to the respective random pulses;

said sampling means using, as said sampled phase lags, phase lags each of which is had by the random read pulse phase of one of said selected read pulse sequences relative to the random write pulse phase of the concurrently selected write pulse sequence.

4. A pulse stuff synchronization device as claimed in claim 1, wherein:

said randomizing means comprises;

means responsive to said write pulse sequences for producing first through (k+1)-th preselected ones of said write pulse sequences having first through (k+1)-th preselected write pulse phases, respectively, said first through said (k+1)-th preselected write pulse phases lagging in the cyclic order or said first through said i-th write pulse sequences behind said first write pulse phase by first through (k+1)-th input bit periods, respectively;

means responsive to said read pulse sequences for producing first through (k+1)-th preselected ones of said read pulse sequences having first through (k+1)-th preselected read pulse phases, respectively, said first through said (k+1)-th preselected read pulse phases lagging in the cyclic order of said first through said i-th read pulse sequences behind said first read pulse phase by first through (k+1)-th output bit periods, respectively, said first through said (k+1)-th output bit periods corresponding to said first through said (k+1)-th input bit periods, respectively, said first through said (k+1)-th preselected read pulse sequences thereby being in one-to-one correspondence to said first through said (k+1)-th preselected write pulse sequences, said first through said (k+1)-th preselected read pulse phases having first through (k+1)-th phase lags relative to said first through said (k+1)-th preselected write pulse phases, respectively; and

means for cyclically supplying said first through said (k+1)-th preselected write and read pulse sequences to said sampling means;

said sampling means cyclically using said first through said (k+1)-th phase lags as said sampled phase lags;

said phase lag monitoring means comprising first through (k+1)-th phase lag monitors for monitoring said first through said (k+1)-th phase lags, respectively, to produce first through (k+1)-th stuff demand pulses, respectively, every time the respective ones of said first through said (k+1)-th phase lags decrease below said predetermined threshold;

said randomizing means further comprising a selector responsive to each of said random pulses for selecting, as one of the stuff demand pulses recited in claim 1, one of said first through said (k+1)-th stuff demand pulses that is serially numbered by a number equal to the number of at least one output bit period of the pulse interval next preceding said each random pulse.

5. A pulse stuff synchronization device as claimed in claim 1, 2, 3, 4, wherein said pulse interval is variable at random among (k+1) values.

6. A pulse stuff synchronization device responsive to an input pulse sequence comprising input information pulses at an input bit rate for producing an output pulse sequence comprising output information pulses and stuff pulses in selected ones of consecutive pulse slots defined by a reference clock pulse sequence of an output bit rate higher than said input bit rate, said consecutive pulse slots being divisible into a succession of frames and including that at least one predetermined pulse slot in each frame in which said output pulse sequence includes a selected one of said output information pulses and said stuff pulses to arrange said input information pulses in said output pulse sequence as the respective output information pulses in synchronism with said reference clock pulse sequence, said device comprising (a) i one-bit memory cells, where i represents a predetermined natural number equal at least to two, (b) means for producing first through i-th write pulse sequences having first through i-th cyclically retarding write pulse phases, respectively, for use in storing said input information pulses cyclically in said memory cells, (c) gapping means responsive to said reference clock pulse sequence and a control pulse produced in one frame for providing a gap between the reference clock pulses at the predetermined pulse slot in a frame next succeeding said one frame to produce a gapped clock pulse sequence in response to successive control pulses, (d) means responsive to said gapped clock pulse sequence for distributing the gapped clock pulses into first through i-th read pulse sequences having first through i-th cyclically retarding read pulse phases, respectively, to produce said first through said i-th read pulse sequences, said first read pulse phase having a phase lag relative to said first write pulse phase, (e) means responsive to said first through said i-th read pulse sequences for cyclically reading as said output information pulses the input information pulses stored in said memory cells, (f) means for sampling phase lags of said first through said i-th read pulse phases relative to said first through said i-th write pulse phases, respectively, to provide sampled phase lags from time to time, (g) phase lag monitoring means coupled to means for monitoring said sampled phase lags to successively produce stuff demand pulses every time said sampled phase lags decrease below a predetermined threshold, said output pulse sequence being subject to a jitter component when said sampled phase lags are sampled at a sampling interval substantially equal to i input bit periods, (h) supplying means for supplying said stuff demand pulses as said successive control pulses to said gapping means, said supplying means comprising:

holding means for holding each of said stuff demand pulses during an interval of time between a pulse slot in said one frame at which said each stuff demand pulse is produced and a pulse slot predetermined relative to said next succeeding frame and means for producing said held stuff demand pulse as said control pulse in the predetermined pulse slot in said next succeeding frame; and

(i) jitter reducing means comprising;

a random pulse generator responsive to said reference clock pulse sequence for producing a sequence of random pulses having a pulse interval variable at random between i and (i-k) output bit periods, both inclusive, where k represents an integer preselected from natural numbers less than said predetermined natural number and means coupled to said holding means and responsive to each of said random pulses for lengthening said interval of time in relation to the pulse interval next preceding said each random pulse.

7. A pulse stuff synchronization device as claimed in claim 6, wherein said pulse interval is variable at random among (k+1) values.

8. A pulse stuff synchronization device responsive to an input pulse sequence comprising input information pulses at an input bit rate for producing an output pulse sequence comprising output information pulses and stuff pulses in selected ones of consecutive pulse slots defined by a reference clock pulse sequence of an output bit rate higher than said input bit rate, said consecutive pulse slots being divisible into a succession of frames and including that at least one predetermined pulse slot in each frame in which said output pulse sequence includes a selected one of said output information pulses and said stuff pulses to arrange said input information pulses in said output pulse sequence as the respective output information pulses in synchronism with said reference clock pulse sequence, said device comprising (a) i one-bit memory cells, where i represents a predetermined natural number equal at least to two, (b) means for producing first through i-th write pulse sequences having first through i-th cyclically retarding write pulse phases, respectively, for use in storing said input information pulses cyclically in said memory cells, (c) gapping means responsive to said reference clock pulse sequence and a control pulse produced in one frame for providing a gap between the reference clock pulses at the predetermined pulse slot in a frame next succeeding said one frame to produce a gapped clock pulse sequence in response to successive control pulses, (d) means responsive to said gapped clock pulse sequence for distributing the gapped clock pulses into first through i-th read pulse sequences having first through i-th cyclically retarding read pulse phases, respectively, to produce said first through said i-th read pulse sequences, said first read pulse phase having a phase lag relative to said first write pulse phase, (e) means responsive to said first through said i-th read pulse sequences for cyclically reading as said output information pulses the input information pulses stored in said memory cells, (f) means for sampling phase lags of said first through said i-th read pulse phases relative to said first through said i-th write pulse phases, respectively, to provide sampled phase lags from time to time, (g) phase lag monitoring means coupled to said sampling means for monitoring said sampled phase lags to successively produce stuff demand pulses every time said sampled phase lags decrease below a predetermined threshold, and (h) supplying means for supplying said stuff demand pulses as said successive control pulses to said gapping means, said output pulse sequence being subject to a jitter component when said sampled phase lags are sampled at a sampling interval substantially equal to i input bit periods, wherein the improvement is characterized in that said predetermined natural number is a selected prime number having a value greater than or equal to three, thereby reducing said jitter component.