Battery-saving arrangement for pagers

• US 4,398,192 A
• Filed: 12/04/1981
• Issued: 08/09/1983
• Est. Priority Date: 12/04/1981
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Moore, Morris A., Braun, William V.
• Primary Examiner(s): YUSKO, DONALD
• Application Number:
  US06/327,308
• Time in Patent Office: 613 Days
• Field of Search: 340/825.44, 340/825.37, 340/311.1, 179/2 EC, 179/2 EB
• US Class Current: 340/7.29
• CPC Class Codes: H04W 52/0229 where the received signal is a wanted signal
• CPC Class Codes: H04W 88/026 using digital address codes
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A pager or other selectively-addressed electronic device powered by a small power cell operates in four different modes and at two power levels, depending on signals received and a timing sequence. The device can stay active continuously, be activated at intervals or remain in a powered-down state. The address code assigned to a particular device would be transmitted at a predetermined time interval following a sync signal, thus the device can be powered-down until the approximate time period in which its address code could be transmitted. The system provides increased channel efficiency since information codes are superimposed on actual address codes, and there is no dead time in a channel while there are address codes waiting to be transmitted. The system is particularly well adapted to time multiplexing.

Claims

1. A battery-saving arrangement for selectively addressable devices and comprising:

transmission means including first means for receiving two-word binary address codes, means for transmitting a sequence of binary signals, means coupled to the receiving means for sorting the received address codes according to predetermined groups of devices, first memory means coupled to the sorting means for storing the sorted address codes by groups, block control means coupled to the first memory means for assembling ones of the sorted and stored address codes into transmission blocks, second memory means coupled to the block control means for storing a first predetermined number of address codes of one of the respective groups of device address codes, first coding means coupled to the block control means for further encoding predetermined ones of the address codes stored in the second memory means, first generator means for generating two-word synchronizing code signals, said synchronizing codes having the same format as the address codes, and including second coding means for selectively further encoding selected ones of the synchronizing code signals, transmission sequence control means coupled to the block control means and to the first generating means for assembling blocks of address codes and synchronizing codes into a sequence and coupled to the transmission means for transmission; and

a plurality of selectively addressable devices, each device including means for receiving the transmission sequence, means for detecting one of the address codes, all of the further encoded address codes and all synchronizing codes, when said codes appear in the transmission sequence, and means for responding to the detection of said one address code.

2. A battery-saving arrangement in accordance with claim 1 wherein the first coding means selectively inverts at least one word of an address code.

3. A battery-saving arrangement in accordance with claim 1 wherein the second coding means selectively inverts at least one word of the synchronizing code.

4. A battery-saving arrangement in accordance with claim 1 and further including second generator means for providing an additional address code when less than a second predetermined number of address codes of one group is stored in the combined first and second memory means, the second predetermined number being not greater than the first predetermined number and not less than two.

5. A battery-saving arrangement in accordance with claim 4 wherein the block control means couples the first address code in each block through the first coding means.

6. A battery-saving arrangement in accordance with claim 5 and wherein the block control means couples the last address code of the address codes of one predetermined group in the combined first and second memories through the first coding means.

7. A battery-saving arrangement in accordance with claim 1 and wherein the sequence includes a normal transmission cycle including a third predetermined number of blocks of synchronizing codes followed by a fourth predetermined number of blocks of address codes, the fourth predetermined number being the number of predetermined groups of devices.

8. A battery-saving arrangement in accordance with claim 7 and wherein the transmission sequence control means couples at least one of the synchronizing codes in each normal transmission cycle from the second coding means for providing a first encoded synchronizing code.

9. A battery-saving arrangement in accordance with claim 8 and wherein the transmission sequence control means couples synchronizing codes from the second coding means for providing blocks of second encoded synchronizing codes in addition to the normal transmission.

10. A battery-saving arrangement in accordance with claim 9 and wherein the blocks of second encoded synchronizing codes are coupled to the transmission means when less than a fifth predetermined number of address codes is stored in one of the first and second memory means.

11. A battery-saving arrangement in accordance with claim 1 and wherein the detecting means of the selectively addressable devices include means for detecting inversions of the words in the address codes and the synchronizing codes, each device further including means for responding to the inverted code words.

12. A battery-saving arrangement in accordance with claim 11 and wherein the addressable devices further include timing means responsive to the synchronizing codes and to address codes having inverted words.

13. A battery-saving arrangement in accordance with claim 1 and wherein the transmission means further includes third memory means coupled to the block control means for storing received address codes in excess of the first predetermined number, and placing said codes in a first-in/first-out queue, and wherein address codes stored in the third memory means are coupled to the second memory means in advance of address codes stored in the first memory means.