Keyboard and display interface adapter architecture

• US 4,398,265 A
• Filed: 09/15/1980
• Issued: 08/09/1983
• Est. Priority Date: 09/15/1980
• Status: Expired due to Term

• Current Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Puhl, Larry C., Connell, Lawrence E.
• Primary Examiner(s): Chan, Eddie P.
• Application Number:
  US06/187,305
• Time in Patent Office: 1,058 Days
• Field of Search: 364/200 MS File, 364/900 MS File, 179/2 EB
• US Class Current: 710/62
• CPC Class Codes: G06F 3/0227 Cooperation and interconnection of the input arrangement with other functional units of a computer G06F3/023 - G06F3/037 take precedence

Abstract

A unique interface adapter is coupled to a microprocessor by a three-wire self-clocking serial data bus for accommodating a twenty-key keyboard and an eight-digit display. The interface adapter includes circuitry for recovering a clock signal and a non-return-to-zero (NRZ) data signal from the data signal transmitted on two forward signal lines of the serial data bus. The NRZ data signal is shifted into a receiving register, where address circuitry decodes the address portion of the data signal to provide a chip select signal and control circuitry decodes the control portion of the data signal to provide a register select signal, read/write signal and bus sense signal. The register select signal determines whether a control register or display register is to be loaded in response to the read/write signal with the data portion of the data signal. The control register signals activate four status indicating LED'"'"'s, apply power to the display, select between a ten or sixteen digit display, enable an audio tone generator and reset a status bit flip-flop. The display register receives two BCD digits which are stored in a display memory. The keys of the keyboard are scanned at the same time digits read-out from the display memory are being applied to the display. The signals identifying the row and column of activated keys are provided in a return signal line of the serial data bus.

Claims

1. Interface adapter circuitry coupled to a plurality of input signals to a display having a plurality of display elements and further coupled to a self-clocking serial data bus having binary first and second forward data signal lines for receiving a binary data signal including data, address and control portions, transmitted from a signal source, the first and second forward data signals transmitted respectively on the first and second forward data signal lines having a first binary state before and after the data signal, the first forward data signal having a second binary state and the second forward data signal having the first binary state for data signal bits having a binary one state, the first forward data signal having the first binary state and the second forward data signal having the second binary state for data signal bits having a binary zero state, and the first and second forward data signals having the second binary state between successive data signal bits, said interface adapter circuitry comprising:

generating means coupled to the first and second forward data signal lines and being responsive to either the second binary state of the first forward data signal and first binary state of the second forward data signal, or responsive to the first binary state of the first forward data signal and the second binary state of the second forward data signal, for generating a clock signal;

latch means for storing and providing an output signal and being coupled to the first and second forward data signal lines for storing and providing a binary one state of the output signal in response to the second binary state of the first forward data signal and the first binary state of the second forward data signal, and storing and providing a binary zero state of the output signal in response to the first binary state of the first forward data signal and the second binary state of the second forward data signal;

receiving register means coupled to the latch means and the clock signal generating means and being responsive to the clock signal for serially receiving the latch means output signal, said received output signals being the binary data signal;

decoding means coupled to the receiving register means for decoding a predetermined address signal in the address portion of the binary data signal in the receiving register means and generating a chip select signal when the predetermined address signal is decoded; and

control means coupled to the decoding means and the receiving register means and being responsive to the chip select signal and the control signal portion of the binary data signal in the receiving register means for generating at least a first or a second control signal;

control register means coupled to the receiving register means and control means and being responsive to the first control signal for receiving the data portion of the binary data signal in the receiving register means, said received data portion including output signals for selecting a predetermined sequence of display elements;

display register means coupled to the receiving register means and control means and being responsive to the second control signal for receiving the data portion of the data signal in the receiving register means, said received data portion including output signals for the display; and

means coupled to the control register means and display register means for applying the display register output signals to the display elements in response to a predetermined one of the control register output signals.

2. The interface adapter circuitry according to claim 1 wherein said applying means includes means for sequentially applying the display register output signals to the display elements.

3. The interface adapter circuitry according to claim 1, wherein said display register means includes a plurality of registers each providing a plurality of output signals for a corresponding display element, a first register coupled to the latch means for serially receiving the data portion of the data signal from the latch means, and the other registers serially coupled to one another for sequentially receiving the first register output signals, and said applying means coupled to the registers for applying the output signals of each register to a corresponding display element.

4. The interface adapter circuitry according to claim 3, further including means coupled to the receiving register means and said other registers for resetting said other registers to a predetermined state in response to a predetermined one of the signals in the data portion of the data signal in the receiving register means.

5. The interface adapter circuitry according to claim 1, wherein said applying means further includes:

memory means providing a plurality of output signals and being coupled to the display register means for storing the display register means output signals; and

means coupled to the memory means for reading out the memory means output signals and applying the read out output signals to the display elements.

6. The interface adapter circuitry according to claim 1, further including status indicating means coupled to the control register means for providing predetermined visual status indications in response to predetermined ones of the control register output signals.

7. The interface adapter circuitry according to claim 1, wherein said serial data bus further includes a return data signal line, and wherein said interface adapter circuitry further includes keyboard means having a plurality of keys arranged in a predetermined number of rows and columns, means coupled to the keyboard means for scanning the rows and columns for activated keys and providing an output signal indicative of a row and column containing an activated key, and transmitting means coupled to the scanning means, decoding means and clock signal generating means and being enabled by the chip select signal to apply the scanning means output signal to the return data signal line in response to the clock signal.

8. The interface adapter circuitry according to claim 7, wherein said transmitting means further includes transmitting register means for storing the scanning means output signal, said transmitting register means responsive to the clock signal for storing the scanning means output signal when the chip select signal is absent and shifting out the stored scanning means output signal line for application to the return data signal when the chip select signal is present.

9. The interface adapter circuitry according to claim 1, wherein said address decoding means is further coupled to a plurality of address signal lines from a second signal source, said second signal source providing the predetermined address signal.

10. The interface adapter circuitry according to claim 1, wherein said interface adapter circuitry further includes means coupled to the latch means and control means and being responsive to a third control signal for logically complementing the latch means output signal received by the receiving register means, said control means being responsive to the control portion of the data signal in the receiving register means for providing the third control signal.

11. The interface adapter circuitry according to claims 1, wherein said control means includes means for disabling said first and second control signals in response to detection of the first binary state of the first and second forward data signals.

12. The interface adapter circuitry according to claims 1 or 7, further including substrate means, said interface adapter circuitry formed of electrical circuit components integrated into the substrate means.

13. The interface adapter circuitry according to claim 10, wherein said complementing means includes means responsive to the third control signal for logically complementing the first and second control signals.