Keyboard and display interface adapter architecture
First Claim
1. Interface adapter circuitry coupled to a plurality of input signals to a display having a plurality of display elements and further coupled to a self-clocking serial data bus having binary first and second forward data signal lines for receiving a binary data signal including data, address and control portions, transmitted from a signal source, the first and second forward data signals transmitted respectively on the first and second forward data signal lines having a first binary state before and after the data signal, the first forward data signal having a second binary state and the second forward data signal having the first binary state for data signal bits having a binary one state, the first forward data signal having the first binary state and the second forward data signal having the second binary state for data signal bits having a binary zero state, and the first and second forward data signals having the second binary state between successive data signal bits, said interface adapter circuitry comprising:
- generating means coupled to the first and second forward data signal lines and being responsive to either the second binary state of the first forward data signal and first binary state of the second forward data signal, or responsive to the first binary state of the first forward data signal and the second binary state of the second forward data signal, for generating a clock signal;
latch means for storing and providing an output signal and being coupled to the first and second forward data signal lines for storing and providing a binary one state of the output signal in response to the second binary state of the first forward data signal and the first binary state of the second forward data signal, and storing and providing a binary zero state of the output signal in response to the first binary state of the first forward data signal and the second binary state of the second forward data signal;
receiving register means coupled to the latch means and the clock signal generating means and being responsive to the clock signal for serially receiving the latch means output signal, said received output signals being the binary data signal;
decoding means coupled to the receiving register means for decoding a predetermined address signal in the address portion of the binary data signal in the receiving register means and generating a chip select signal when the predetermined address signal is decoded; and
control means coupled to the decoding means and the receiving register means and being responsive to the chip select signal and the control signal portion of the binary data signal in the receiving register means for generating at least a first or a second control signal;
control register means coupled to the receiving register means and control means and being responsive to the first control signal for receiving the data portion of the binary data signal in the receiving register means, said received data portion including output signals for selecting a predetermined sequence of display elements;
display register means coupled to the receiving register means and control means and being responsive to the second control signal for receiving the data portion of the data signal in the receiving register means, said received data portion including output signals for the display; and
means coupled to the control register means and display register means for applying the display register output signals to the display elements in response to a predetermined one of the control register output signals.
1 Assignment
0 Petitions
Accused Products
Abstract
A unique interface adapter is coupled to a microprocessor by a three-wire self-clocking serial data bus for accommodating a twenty-key keyboard and an eight-digit display. The interface adapter includes circuitry for recovering a clock signal and a non-return-to-zero (NRZ) data signal from the data signal transmitted on two forward signal lines of the serial data bus. The NRZ data signal is shifted into a receiving register, where address circuitry decodes the address portion of the data signal to provide a chip select signal and control circuitry decodes the control portion of the data signal to provide a register select signal, read/write signal and bus sense signal. The register select signal determines whether a control register or display register is to be loaded in response to the read/write signal with the data portion of the data signal. The control register signals activate four status indicating LED'"'"'s, apply power to the display, select between a ten or sixteen digit display, enable an audio tone generator and reset a status bit flip-flop. The display register receives two BCD digits which are stored in a display memory. The keys of the keyboard are scanned at the same time digits read-out from the display memory are being applied to the display. The signals identifying the row and column of activated keys are provided in a return signal line of the serial data bus.
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Citations
13 Claims
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1. Interface adapter circuitry coupled to a plurality of input signals to a display having a plurality of display elements and further coupled to a self-clocking serial data bus having binary first and second forward data signal lines for receiving a binary data signal including data, address and control portions, transmitted from a signal source, the first and second forward data signals transmitted respectively on the first and second forward data signal lines having a first binary state before and after the data signal, the first forward data signal having a second binary state and the second forward data signal having the first binary state for data signal bits having a binary one state, the first forward data signal having the first binary state and the second forward data signal having the second binary state for data signal bits having a binary zero state, and the first and second forward data signals having the second binary state between successive data signal bits, said interface adapter circuitry comprising:
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generating means coupled to the first and second forward data signal lines and being responsive to either the second binary state of the first forward data signal and first binary state of the second forward data signal, or responsive to the first binary state of the first forward data signal and the second binary state of the second forward data signal, for generating a clock signal; latch means for storing and providing an output signal and being coupled to the first and second forward data signal lines for storing and providing a binary one state of the output signal in response to the second binary state of the first forward data signal and the first binary state of the second forward data signal, and storing and providing a binary zero state of the output signal in response to the first binary state of the first forward data signal and the second binary state of the second forward data signal; receiving register means coupled to the latch means and the clock signal generating means and being responsive to the clock signal for serially receiving the latch means output signal, said received output signals being the binary data signal; decoding means coupled to the receiving register means for decoding a predetermined address signal in the address portion of the binary data signal in the receiving register means and generating a chip select signal when the predetermined address signal is decoded; and control means coupled to the decoding means and the receiving register means and being responsive to the chip select signal and the control signal portion of the binary data signal in the receiving register means for generating at least a first or a second control signal; control register means coupled to the receiving register means and control means and being responsive to the first control signal for receiving the data portion of the binary data signal in the receiving register means, said received data portion including output signals for selecting a predetermined sequence of display elements; display register means coupled to the receiving register means and control means and being responsive to the second control signal for receiving the data portion of the data signal in the receiving register means, said received data portion including output signals for the display; and means coupled to the control register means and display register means for applying the display register output signals to the display elements in response to a predetermined one of the control register output signals. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13)
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Specification