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Fabrication method for high power MOS device

  • US 4,398,339 A
  • Filed: 09/09/1981
  • Issued: 08/16/1983
  • Est. Priority Date: 04/15/1977
  • Status: Expired due to Fees
First Claim
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1. In a method of fabricating a high power MOS semiconductor device comprising the steps of:

  • forming a substantially V-shaped groove in a semiconductor substrate through both a high conductivity region of one conductivity type and a region of opposite type conductivity that surrounds a substantial portion of said high conductivity region of one conductivity type,forming a first insulating layer in said V-shaped groove,forming a doped electrically conductive polysilicon gate electrode layer on the surface of said first insulating layer,forming a second insulating layer on said polysilicon gate electrode layer,forming an opening in said second insulating layer to expose a surface portion of said polysilicon gate electrode layer,depositing electrical contacts to make separate source and drain connections to regions of said semiconductor substrate and to make electrical contact to said polysilicon gate electrode layer through said opening in said second insulating layer, one of said electrical contacts being located on said second insulating layer.

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