Fabrication method for high power MOS device

• US 4,398,339 A
• Filed: 09/09/1981
• Issued: 08/16/1983
• Est. Priority Date: 04/15/1977
• Status: Expired due to Fees

• Current Assignee: Supertex Incorporated (Microchip Technology Incorporated)
• Original Assignee: Supertex Incorporated (Microchip Technology Incorporated)
• Inventors: Blanchard, Richard A., Choy, Benedict C. K.
• Primary Examiner(s): Andrews, M. J.
• Assistant Examiner(s): Saba, W. G.
• Application Number:
  US06/300,474
• Time in Patent Office: 706 Days
• Field of Search: 29/571, 29/578, 29/580, 29/591, 357/23, 357/55, 357/59, 156/648
• US Class Current: 438/271
• CPC Class Codes: H01L 23/485 consisting of layered constructions comprising conductive layers and insulating layers, e.g. planar contacts H01L23/4821, H01L23/4822, H01L23/4824, H01L23/4825 take precedence; materials H01L23/532, bond pads H01L24/02, bump connectors H01L24/10
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/4236 within a trench, e.g. trench gate electrode, groove gate electrode
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/3011 Impedance

Abstract

This disclosure relates to a high power VMOS semiconductor device and fabrication method therefor. This VMOS semiconductor device uses a doped polysilicon gate electrode in the V groove and an overlying metal electrode located over an insulation layer protecting the doped polysilicon gate electrode. This overlying metal electrode layer covers substantially the entire surface area (except for a small area where electrical contact is made to the doped polysilicon gate electrode) of one surface of the device. Another embodiment discloses the use of a self-aligned metal contact to the source or drain region of the VMOS device between adjacent V groov

Claims

1. In a method of fabricating a high power MOS semiconductor device comprising the steps of:

forming a substantially V-shaped groove in a semiconductor substrate through both a high conductivity region of one conductivity type and a region of opposite type conductivity that surrounds a substantial portion of said high conductivity region of one conductivity type,

forming a first insulating layer in said V-shaped groove,

forming a doped electrically conductive polysilicon gate electrode layer on the surface of said first insulating layer,

forming a second insulating layer on said polysilicon gate electrode layer,

forming an opening in said second insulating layer to expose a surface portion of said polysilicon gate electrode layer,

depositing electrical contacts to make separate source and drain connections to regions of said semiconductor substrate and to make electrical contact to said polysilicon gate electrode layer through said opening in said second insulating layer, one of said electrical contacts being located on said second insulating layer.

2. The method of claim 1 wherein said source electrical contact being deposited over substantially the entire surface of said second and first insulating layers formed on one surface of said semiconductor substrate except for the surface portion containing the electrical contact to said polysilicon gate electrode layer, and said drain electrical contact being deposited in contact with a region of said semiconductor substrate along the opposite surface of said semiconductor substrate.

3. The method of claim 2 wherein said source electrical contact being in electrical contact to both a portion of said high conductivity region of one conductivity type forming the source region and a region opposite type conductivity forming part of a channel region through an opening in said first insulating layer.

4. The method of claim 2 including the steps of depositing said source electrical contact by first evaporating a thin layer of one metal followed by plating a thicker layer of another metal to provide a large heat sink.

5. In a method of fabricating a high power MOS semiconductor device comprising the steps of:

forming a pair of spaced substantially V-shaped grooves in a semiconductor substrate through both a high conductivity region of one conductivity type and a region of opposite type conductivity that surrounds a substantial portion of said high conductivity region of one conductivity type,

forming a first insulating layer in said substantially V-shaped grooves,

forming a second insulating layer in said substantially V-shaped grooves,

forming a doped electrically conductive polysilicon gate electrode layer on the surface of said second insulating layer in each of said pair of substantially V-shaped grooves,

forming a third insulating layer on said polysilicon gate electrode layer,

forming an opening in said third insulating layer to expose a surface portion of said polysilicon gate electrode layer, and

depositing electrical contacts to make separate source and drain connections to regions of said semiconductor substrate and to make separate electrical contact to said polysilicon gate electrode layer through said opening in said third insulating layer, one of said electrical contacts being located on said third insulating layer.

6. The method of claim 5 wherein the first insulating layer being silicon dioxide and said second insulating layer being silicon nitride.

7. The method of claim 5 wherein one of said deposited electrical contacts contacting said semiconductor substrate between said pair of spaced V-shaped grooves.

8. The method of claim 5, wherein said step of forming said third insulating layer on said polysilicon gate electrode layer comprising growing said insulating layer from said polysilicon gate electrode layer.

9. The method of claim 5 further including the step of forming the deposited electrical contacts to provide a source contact over substantially all of said polysilicon gate electrode layer and in said grooves.

10. The method of claim 8 further including the step of forming the deposited electrical contacts to provide a source contact over substantially all of said polysilicon gate electrode layer and in said grooves.