Digital tone generator

• US 4,399,535 A
• Filed: 06/18/1981
• Issued: 08/16/1983
• Est. Priority Date: 06/18/1981
• Status: Expired due to Fees

• Current Assignee: Siemens Corp. (Siemens AG)
• Original Assignee: Siemens Corp. (Siemens AG)
• Inventors: Southard, Gary D.
• Primary Examiner(s): Olms, Douglas W.
• Application Number:
  US06/275,146
• Time in Patent Office: 789 Days
• Field of Search: 370/110.2, 179/84 VF, 179/18 J, 179/99 M
• US Class Current: 370/525
• CPC Class Codes: H04Q 1/4575 which are transmitted in digital form

Abstract

A digital tone generator for use with a digital telecommunication system for simultaneous generation of continuous and cyclically repeated discontinuous tone signals each composed of at least one frequency component incorporates sequencing control means, amplitude control means, amplitude value generating means and output means. The sequencing control means generates consecutively incremented reference address signals directing the course of an operating cycle, thus allowing for some amount of parallel processing of the sub-units. The amplitude control means produce amplitude control signals which determine varying mean amplitude values of a discontinuous digital tone signal at the commencement of the rising and trailing ends of each pulse. Any stepwise adjustment of the mean amplitude value takes place coincidentally with an instantaneous amplitude of zero value and in accordance with a predetermined attenuation curve. The amplitude value generating means connected to receive the reference address signals and the amplitude control signals furnish a digital encoded signal representing an instantaneous amplitude value of a respective digital signal to output means for transmitting the same onto a time multiplexed transmission line.

Claims

1. A digital tone generator adapted to be connected to a digital telecommunication system for simultaneously generating during a tone generator operation cycle digital encoded instantaneous amplitude values of a variety of continuous and of cyclically repeated discontinuous tone signals each composed of at least one frequency component and assigned to a separate tone channel of a tone highway representing a time-division multiplexed serial data transmission line, said digital tone generator comprising:

(a) sequencing control means for generating a consecutively incremented and cyclically repeated reference address signal directing the course of said operating cycle;

(b) amplitude control means for generating amplitude control signals determining varying mean amplitude values of discontinuous digital tone signals such that stepwise adjusting of a mean amplitude value takes place coincidentally with the instantaneous amplitude going through zero value and in accordance with a predetermined attenuation curve at the commencement of the rising and trailing ends of a pulse of each discontinuous digital tone signal, said amplitude control means including at least one input connected to receive said reference address signal, storage means for storing steady and variable amplitude control information, processing means for producing said amplitude control signals, and at least one input;

(c) amplitude value generating means including a phase value generator connected to receive said reference signal for producing an instantaneous, frequency dependent phase value signal constituting a current sine address signal; and

including a single sine wave generator incorporating a sine wave memory in form of a random access memory provided with a multiplicity of memory locations each permanently storing one of consecutive sine amplitude values having a finite difference from each other such that these values represent a continuous part of a single sine wave form, said memory for storing sine wave amplitude values having address inputs connected to receive the sine address signal and read outputs wherein said amplitude value generating means are further connected to receive said amplitude control signals for generating a digital encoded signal representing one of said instantaneous amplitude values; and

(d) output means connected to receive said digital encoded signals for transmitting said digital encoded signal onto said tone highway in synchronization with the cyclical occurrence of the assigned tone channel.

2. The digital tone generator as recited in claim 1, further comprising:

a first unidirectional bus connecting said sequencing unit to said amplitude control means and said amplitude value generating means for transmitting all bits of said reference address signal in parallel.

3. The digital tone generator as recited in claim 1, wherein the sequencing control means further comprises:

a clock generator composed of a frequency dividing binary counter arrangement having a clock input for receiving an external master clock signal, a reset input for receiving a main synchronization signal and a plurality of parallel outputs for high frequency and low frequency pulse trains;

said outputs for low frequency pulse trains furnishing in parallel all bits of said reference address signal at a time, wherein the least significant bits of said reference address signal determine in combination consecutive reference addresses each associated with a respective one of said frequency components of a tone signal; and

a steering signal generator connected to receive in parallel the high frequency pulse trains including said least significant bits of the reference address signal, said steering signal generator including a storage arrangement being cyclically addressed for reading operations by means of the received clock generator output signals and having parallel outputs supplying steering signals controlling the synchronized step-by-step operation of the digital tone generator for generating said digital encoded signals.

4. The digital tone generator as recited in claim 1, wherein said amplitude value generating means further comprise:

an attenuating unit connected to the read outputs of the sine wave generator and connected to receive the amplitude control signals and being adjustable to attenuate a received sine amplitude value into an attenuated sine amplitude signal, wherein the attenuation rate is determined in accordance with the present amplitude control signals; and

a processing circuitry network connected to receive said attenuated sine amplitude signal for generating the corresponding digital encoded instantaneous amplitude value by summing consecutive attenuated sine wave amplitude signals each corresponding to a different frequency component of one of said tone signals.

5. The digital tone generator as recited in claim 4, wherein said phase value generator comprises:

a read-only phase constant memory having address inputs connected to receive the reference frequency address, data outputs, and memory locations each storing an individual frequency dependent phase constant determined to define a relative address difference for the sine wave memory and corresponding to a respective frequency component of one of said tone signals;

a randomly accessible phase value memory for intermediately storing current phase values each corresponding to a respective bit combination of the reference address signal, said phase value memory having address inputs connected to receive the reference address signal, data inputs and data outputs; and

said data outputs of said phase constant memory and of said phase value memory being connected to said inputs of said processing circuitry network enabling summing of simultaneously occurring respective memory output signals to generate a subsequent phase value signal furnished to the sine wave generator and stored back into the phase value memory.

6. The digital tone generator as recited in claim 4, wherein said sine wave generator further comprises:

an address buffer having parallel inputs connected to receive said phase value signal, parallel outputs connected to said address inputs of said sine wave memory and a control input connected to receive a respective one of said steering signals for synchronizing address select and read operations of the sine wave memory with the time frame of the digital tone generator.

7. The digital tone generator as recited in claim 6, wherein the phase value signal is composed of (n=2) bits with n bits forming an address of the sine wave generator memory and two most significant bits representing a sign bit and a quadrant bit, respectively, and wherein the sine wave generator further comprises:

a multiple exclusive-OR circuit having n circuits each associated with a respective one of n less significant bits of the phase value signal;

each exclusive OR circuit having a first input connected to receive a respective bit of the phase value signal, a second input connected to receive the quadrant bit and an output connected to a respective one of the parallel inputs of the address buffer for storing a sine address signal; and

a read only memory forming said sine wave memory and being composed of memory locations storing sine wave amplitude values for just one quadrant of the sine wave form.

8. The digital tone generator as recited in claim 7, wherein the read only memory of the sine wave generator further comprises:

two memory areas each storing an alternatively selectable table of sine amplitude values representing one quadrant of a sine wave form but differing from each other by 3 db; and

a further address input for selecting a respective one of said memory areas and connected to receive one of said amplitude control signals forming a table select signal, whereby in combination with the operation of said attenuating unit attenuated sine amplitude values differing from each other in 3 db steps can be obtained.

9. The digital tone generator as recited in claim 8, wherein the attenuating unit is a shift logic unit composed of shift matrices for performing a selectable number of shift operations on a received sine amplitude value under control of said amplitude control signals representing a shift step number code.

10. The digital tone generator as recited in claim 9, wherein the processing circuitry network comprises:

an arithmetical unit having a first set of parallel inputs for receiving a first operand, a second set of parallel inputs for receiving a second operand and a set of parallel outputs; and

first, second and third buffer registers each having parallel inputs and outputs, said first buffer registers each connected to receive the attenuated sine amplitude value associated with a respective one of the frequency components of the same tone signal and having outputs connected to a respective one of the sets of parallel inputs of the arithmetic logical unit;

said second buffer register connected by its inputs to the outputs of the arithmetic logical unit and by its outputs to one set of inputs of the arithmetic logical unit for buffering an intermediate result of a summing operation of attenuated sine amplitude values associated with different frequency components of the same tone signal; and

said third buffer register connected by its inputs to the outputs of the arithmetic logical unit for storing the digital encoded instantaneous amplitude value representing the final result of the summing operations with respect to all different frequency components of the same tone signal.

11. The digital tone generator as recited in claim 10, wherein the means for consecutively generating amplitude control signals with respect to predetermined cadence patterns designating a cyclically repeated timing pattern of a discontinuous tone specifying changes in mean amplitude, frequency combination as a function of time comprises:

a cadence select memory having data outputs and address inputs connected to receive said reference address signal for selecting a cadence address and a final amplitude level code of a respective one of said cadence patterns;

a cadence control processing system connected to receive said cadence address for generating status information representing a current signal condition in the course of the respective cadence pattern; and

a gain control unit connected to receive the reference address signal, the status information, the final amplitude level code and the current sign bit each corresponding to the same discontinuous tone, said gain control unit adapted for monitoring the status information in regard to a change of the respective cadence pattern, and for generating adjusted amplitude control signals upon initialization by a changing sign bit during a ramp-up and a ramp-down period, said adjusted amplitude control signals including the table select signals and an attenuation control signal representing the shift step number code, wherein any adjustment of the combination of said adjusted amplitude control signal occurs just prior to the respective sine amplitude value becoming zero.

12. The digital tone generator as recited in claim 11, wherein the cadence control processing system comprises:

a microprocessor having an interrupt connected to receive said main synchronizing signal for synchronizing the start of a cadence control cycle of the microprocessor with the operation cycle of the sequencing control means, the microprocessor having an input port and an output port and being determined to monitor in one cadence control cycle the course of each cadence and to generate correspondingly updated status information with respect to each cadence and a cadence cycle signal after updating all cadences;

a cadence read only memory forming a external memory of the microprocessor for storing of time constants and further control information for individually activating frequency components each associated with a respective cadence; and

a system random access memory having data inputs connected to receive the status information from the microprocessor output port for buffering and being accessible for a read operation by means of the cadence address for selecting currently stored status information of the respective cadence; and

having data outputs connected to said gain control unit.

13. The digital tone generator as recited in claim 12, wherein the system random access memory is composed of two separate system memory banks having address inputs, data inputs connected to receive the status information generated by the microprocessor, data outputs and write enable inputs, and being alternately assigned to the microprocessor for storing current status information with respect to each cadence, on the one hand, and to the cadence select memory and the gain control unit, on the other hand, for reading previously stored status information;

and wherein the cadence control processing system further comprises a multiple switch for alternately connecting the address inputs of one system memory bank to the outputs of the cadence select PROM, the data outputs of the same system memory bank to the gain control unit and the address inputs and the write enable input of the other system memory bank to the microprocessor; and

a toggle flip-flop having a clock input connected to receive the main synchronizing signal, a data input connected to receive the cadence cycle signal generated by the microprocessor and a control output connected to the multiple switch for passing a switch control signal causing the state of the multiple switch to be reversed into the alternate switch position.

14. The digital tone generator as recited in claim 13, wherein each system memory bank is composed of memory locations each associated with one cadence for storing status information including an individual frequency select flag for each of the frequency components and a cadence enable bit representing the current on and off condition of the cadence;

and said frequency select flags indicating by their states the presently active condition of the respective frequency component and the de-activated condition, respectively.

15. The digital tone generator as recited in claim 12, wherein the cadence patterns are divided into consecutive cadence steps each representing a part of the pulse pattern including just one change of a pattern variable at the beginning of a step and correspondingly the cadence read only memory further comprises:

a plurality of memory blocks each associated with a respective one of the cadences and including memory locations for a respective memory word each assigned to one cadence step and accommodating a first group of bit positions for storing a time constant designating the duration of the cadence step in terms of a number of cadence control cycles, accommodating a second bit group representing frequency select bits each designating the state of a respective frequency component during the corresponding cadence step and accommodating a cadence enable bit specifying the currently active condition of the cadence and de-activated condition, respectively.

16. The digital tone generator as recited in claim 15, wherein besides cadence patterns similar dial pulse patterns are provided, and the cadence read only memory further comprises memory locations each for storing a corresponding step of the dial pulse pattern and including a first bit group for storing a further time constant designating the duration of a respective dial pulse step and a secod bit group designated for dial pulse status bits representing information of the dial pulse step.

17. The digital tone generator as recited in claim 16, wherein the cadence read only memory comprises a further bit group in each memory location associated with a cadence step, said further bit group combination representing a code determining a respective one of software flags each associated with a specific cadence, and

wherein selected lines of the microprocessor'"'"'s output port are fixedly allocated for generating output signals corresponding to one of the cadence software flags and one of the dial pulse status bits, respectively;

and

said output signals are adapted to be separately transmitted to a centrally located processing unit of a digital telecommunication system to serve as control signals with duty cycle time constants differing from the respective tone cadence to provide a guard time eliminating access and operation time delays in the centrally located processing unit.

18. The digital tone generator as recited in claim 14, wherein the gain control unit comprises:

a one-out-of-m selector device having m parallel data inputs each connected to receive a respective one of the frequency select flags, selector inputs connected to receive the least significant bits of the reference address signal for selecting, in combination, one data input, and an output carrying the frequency select flag at the selected data input;

a randomly accessible ramp memory for storing the bit combination of the amplitude control signals each associated with a respective frequency component of a digital tone signal for one tone generator operating cycle, said ramp memory having address inputs for receiving the reference address signal, data inputs and data outputs; and

a ramp control memory designed as read only memory and composed of a plurality of memory locations each storing a combination of said amplitude control signals including a bit group representing the shift step number code, a bit rendering the table select signal, a bit representing the current sign bit and an idle channel code bit;

said ramp control memory having data outputs and parallel address inputs, including a first group of address inputs connected to respective cadence select memory outputs providing the final amplitude level code, a second group of address inputs connected to the data outputs of the ramp memory, another address input connected to the output of the selector device and a further address input to receive the sign bit associated with the currently present sine wave generator address.

19. The digital tone generator as recited in claim 1, wherein said output means comprises:

a compander including inputs connected to receive the digital encoded signal and outputs and being adapted to modify the signal representation of said digital encoded signal; and

a parallel-to-series converter having parallel inputs connected to said outputs of said compander and a serieal output adapted to be connected to said tone highway.

20. The digital tone generator as recited in claim 19, wherein said output means further comprises a second attenuating unit arranged between said compander and said parallel-to-series converter and accommodating fine adjustment of the amplitude level of the digital encoded signal received from said compander by attenuating the same in one and two db steps, respectively.

21. The digital tone generator as recited in claim 20, wherein said output means being adapted to be connected to two tone highways further comprise a further parallel-to-series converter having parallel inputs arranged in parallel to said inputs of said parallel-to-series converter and a serial output adapted to be connected to said second tone highway;

and both parallel-to-series converters including a select enable input for being alternately selectable for receiving consecutive digital tone signals.