Thin film semiconductor device and method for manufacture

• US 4,400,715 A
• Filed: 11/19/1980
• Issued: 08/23/1983
• Est. Priority Date: 11/19/1980
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Barbee, Steven G., Nagarajan, Arunachala, Lloyd, James R., Leas, James M.
• Primary Examiner(s): Edlow, Martin H.
• Application Number:
  US06/208,442
• Time in Patent Office: 1,007 Days
• Field of Search: 357/55, 357/49, 357/4
• US Class Current: 257/74
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02587 Structure
• CPC Class Codes: H01L 21/02598 monocrystalline
• CPC Class Codes: H01L 21/0262 Reduction or decomposition of gaseous compounds, e.g. CVD
• CPC Class Codes: H01L 21/02675 using laser beams
• CPC Class Codes: H01L 21/02689 using particle beams
• CPC Class Codes: H01L 21/02691 Scanning of a beam
• CPC Class Codes: H01L 21/743 Making of internal connections, substrate contacts
• CPC Class Codes: H01L 21/8221 Three dimensional integrated circuits stacked in different levels
• CPC Class Codes: H01L 23/481 Internal lead connections, e.g. via connections, feedthrough structures
• CPC Class Codes: H01L 29/04 characterised by their crystalline structure, e.g. polycrystalline, cubic or particular orientation of crystalline planes characterised by physical imperfections H01L29/30
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
• CPC Class Codes: H01L 2924/09701 Low temperature co-fired ceramic [LTCC]

Abstract

A process for the preparation of a semiconductor device in a thin film of a monocrystalline semiconductor material supported on the surface of a substrate. In the process a thin film of a monocrystalline semiconductor material is formed on a substrate. The film of monocrystalline semiconductor material is doped at various depths with various types and concentrations of dopants. Thereafter, contacts are established at various depths of the doped thin film. In one embodiment, a thin film of a non-monocrystalline semiconductor material is deposited on a substrate. The thin film of non-monocrystalline semiconductor material is doped in situ as it is being deposited with various doping impurities to provide various types and concentrations of doping impurities at various depths. The thin film of non-monocrystalline semiconductor material has at least one tapered region terminating in a point. The thin film of non-monocrystalline semiconductor material is traversed with a particle beam. The traverse is initiated at the point causing nucleation of a crystal at the point and subsequent growth of a monocrystalline thin film of semiconductor material from the point during the traverse. Contacts are then established at various depths to provide a semiconductor device, such as a bipolar transistor.

Claims

1. A thin film semiconductor device comprising:

a substrate including at least one surface which is of a insulating dielectric material, a plurality of overlying layers of doped monocrystalline semiconductor material united to the insulating dielectric material, said doped monocrystalline layers being converted doped polycrystalline semiconductor material, a plurality of circuit elements in the layers, selected trenches isolating the circuit elements from each other, an insulating layer on the surface of the overlying layers and on the vertical surfaces of the trenches, and a metallization pattern contacting the circuit elements through the remaining trenches whereby a full dielectric isolation of the circuit elements is achieved in the device.

2. The device of claim 1 wherein the substrate consists of polycrystalline silicon the surface of which being covered by a blanket dielectric layer with low fixed charge.

3. The device of claim 1 or 2 wherein the plurality of overlying layers comprises three layers of silicon;

the first layer having a varying level of N type dopant;

the second layer being doped with a P type dopant, and

the third layer being doped with a high level of N type dopant

whereby the three layers form the subcollector, base and emitter of a transistor structure.

4. The device of claim 3 wherein the doping profile of the first layer for the subcollector is tailored to provide a low doping level near the base and a higher doping level near the substrate.

5. The device of claim 1 further comprising platinum silicide contacts connected to at least part of said metallization pattern.

6. The device of claim 1, 2, 4, or 5 further comprising additional levels of full dielectric isolated circuit elements atop of each other, the dielectric material of an overlying level being adjacent to the metallization pattern of an underlying level, whereby three dimensional multilevel device arrays are provided.

7. The device of claim 6 further comprising a polysilicon filling of the isolation trenches of the individual device structures.