Automatic test system utilizing interchangeable test devices

• US 4,402,055 A
• Filed: 01/27/1981
• Issued: 08/30/1983
• Est. Priority Date: 01/27/1981
• Status: Expired due to Fees

• Current Assignee: Westinghouse Electric Company LLC (Brookfield Asset Management Incorporated)
• Original Assignee: Westinghouse Electric Company LLC (Brookfield Asset Management Incorporated)
• Inventors: Lloyd, Raymond A., Reeder, James R., Tate, Allen W. Jr., Charles, Larry L., Susie, William F.
• Primary Examiner(s): Wise, Edward J.
• Application Number:
  US06/229,029
• Time in Patent Office: 945 Days
• Field of Search: 364/579, 364/580, 364/900, 364/200, 371/20, 324/73 R, 324/73 AT
• US Class Current: 702/121
• CPC Class Codes: G01R 31/2834 Automated test systems [ATE]; using microprocessors or computers G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation
• CPC Class Codes: G01R 31/31907 Modular tester, e.g. controlling and coordinating instruments in a bus based architecture
• CPC Class Codes: G01R 31/31912 Tester/user interface
• CPC Class Codes: G01R 31/31926 Routing signals to or from the device under test [DUT], e.g. switch matrix, pin multiplexing
• CPC Class Codes: G06F 2201/865 Monitoring of software

Abstract

An automatic test system controlled by a general purpose digital central processor is disclosed. The central processor accepts test programs in a high level compiler language such as Atlas. The Atlas program is compacted into a simplified language which is utilized to communicate with test devices via a standard IEEE 488 data bus. Each of the test devices includes a programmable interface digital processor which performs any translation that may be necessary in order to permit specific test instruments coupled to the central processor via the interface processor to perform the tests specified by the high level test programs. A switching matrix also communicates with the digital processor to connect the appropriate test device to the unit under test.

Claims

1. A test system, comprising in combination:

a. a central programmable digital processor for accepting a test program in a first high level compiler language, said program comprising a plurality of program sequences each specifying a test to be performed on a unit under test;

b. a plurality of test devices each including a programmable processor and at least one test instrument coupled to communicate with said programmable digital processor via a data bus using a compacted (i.e. simplified version) of said high-level compiler language;

c. a switch matrix coupled to receive switching commands from said programmable digital processor via a data bus and the data input/output line from said test devices;

wherein

d. each sequence of said program in said first high level compiler language specifying a test to be performed is compacted by said programmable digital processor to produce program sequences in said compact version of said first high level compiler language with portions of said program sequences in said compact version of said high level compiler language relating to one of said test instrument being coupled to said programmable processor comprising a portion of at least one of said plurality of test devices which in response thereto generates the signals required by said at least one test instrument to perform the specified test and to said switch matrix to couple said at least one test instrument to said apparatus to be tested.

2. A test system in accordance with claim 1 wherein each of said test devices includes a programmable digital processor.

3. A test system in accordance with claim 2 wherein each of said programmable digital processors are coupled to said central processor to selectively receive instructions from said central processor and in response thereto control a specific test instrument causing said specific test instrument to perform test specified thereby and couple the results of said test to said central processor.

4. A test system in accordance with claim 3 wherein said switching matrix includes a programmable digital processor for receiving instructions from said central processor and in response thereto coupling one of said test devices to apparatus to be tested.

5. A test device for use in an automatic test system, said test system being controlled by a central programmed digital processor utilizing program sequences in a high level compiler language;

said test device comprising;

a. a first interface unit for coupling to the data bus of said central programmed processor;

b. a programmable digital processor coupled to communicate with said central programmable digital processor via said first interface unit;

c. a digitally controlled test instrument; and

d. a second interface unit coupling said programmable digital processor to said digitally controlled test instrument.

6. A test device in accordance with claim 5 wherein said interface processor includes a read only memory for storing programs.

7. A test device in accordance with claim 6 wherein said programmable digital processor includes a read/write memory for data processing.

8. A test system in accordance with claim 7 wherein said read only memory is a random access memory.

9. A test device in accordance with claim 8 wherein said read/write memory is a random access memory.