FM Stereo demodulation circuit with voltage dividing and multiplexing techniques

• US 4,404,430 A
• Filed: 11/20/1981
• Issued: 09/13/1983
• Est. Priority Date: 11/28/1980
• Status: Expired due to Fees

• Current Assignee: Nippon Yusen Kabushiki Kaisha
• Original Assignee: Nippon Yusen Kabushiki Kaisha
• Inventors: Ogita, Minoru
• Primary Examiner(s): Hickey, R. J.
• Application Number:
  US06/323,374
• Time in Patent Office: 662 Days
• Field of Search: 179/1 GB, 179/1 GC, 179/1 GD, 179/1 GN, 179/1 GM, 179/1 P, 179/1 GE, 363/43, 363/148, 363/156, 328/14, 328/162, 328/165, 329/122, 329/123, 329/124
• US Class Current: 381/7
• CPC Class Codes: H03D 1/2236 using a phase locked loop
• CPC Class Codes: H04H 40/63 for separation improvements or adjustments

Abstract

An FM stereo demodulation circuit comprises a resistor voltage dividing network having a plurality of outputs; a first switch circuit having a plurality of analog switches which respectively couple the outputs of the voltage dividing network to a first output terminal; a second switch circuit having a plurality of analog switches which respectively couple the outputs of the voltage dividing network to a second output terminal; and a switch control circuit which sequentially enables the analog switches of the first and second switch circuits over one cycle period of a subscarrier signal in response to a pilot signal in an FM stereo composite signal. The circuits produce a staircase-wave multiplying signal having a waveshape which depends on the setting of the resistance values of resistors of the voltage dividing network. The FM stereo composite signal having the pilot signal therein or the pilot signal removed therefrom prior to demodulation is applied to the voltage dividing network so that the FM stereo composite signal is multiplied by the multiplying signal to accomplish the FM stereo demodulation.

Claims

1. An FM stereo demodulation circuit comprising:

a voltage dividing network connected to receive an FM stereo composite signal which contains a pilot signal of half the frequency of a subcarrier, said voltage dividing network having plurality of outputs which provide a plurality of different voltage levels;

a first switch circuit having a plurality of analog switches for respectively coupling said outputs of said voltage dividing network to a first output terminal;

a second switch circuit having a plurality of analog switches for respectively coupling said outputs of said voltage dividing network to a second output terminal; and

analog switch control circuit means responsive to the pilot signal for scanning said analog switches of said first and second switch circuits such that said analog switches of each of said first and second switch circuits are sequentially enabled in a reciprocating manner over one cycle period of said subcarrier and a switch scan cycle of said first switch circuit is 180°

out of phase with that of said second switch circuit.

3. An FM stereo demodulation circuit according to claim 1 or 2, wherein said voltage dividing network is a resistor voltage dividing circuit having a plurality of resistors of an equal resistance value.

4. An FM stereo demodulation circuit according to claim 1 or 2, wherein said voltage dividing network is a resistor voltage dividing circuit having a plurality of resistors which have resistance values symmetrical with respect to a resistor which is located at a center of said plurality of resistors.

5. An FM stereo demodulation circuit according to claim 1 or 2, wherein said analog switch control circuit means comprises

a voltage-controlled oscillator for producing a first clock signal having a frequency which is an integral multiple of the subcarrier frequency;

and up-down counter having an up-down control input for counting the first clock signal produced by said voltage-controlled oscillator, said up-down counter providing an output in the form of a binary-coded decimal (BCD) code;

a BCD/decimal decoder having outputs coupled to said analog switches of each of said first and second switch circuits for decoding a binary-coded decimal code output of said up-down counter;

means for generating a second clock signal having the same frequency as the subcarrier frequency in response to outputs of said BCD/decimal decoder, the second clock signal being applied to said up-down control input of said up-down counter;

means for producing a third clock signal having the same frequency as the pilot signal by frequency-dividing the second clock signal; and

a phase comparator for comparing in phase the third clock signal with the pilot signal in the FM stereo composite signal to control an oscillation frequency of said voltage-controlled oscillator.

2. An FM stereo demodulation circuit comprising:

pilot signal eliminating circuit means for eliminating a pilot signal from an FM stereo composite signal which has the pilot signal of half a frequency of a subcarrier;

a voltage dividing network connected to receive an output signal of said pilot signal eliminating circuit means, said voltage dividing network having a plurality of outputs which provide a plurality of different voltage levels;

a first switch circuit having a plurality of analog switches for respectively coupling said outputs of said voltage dividing network to a first output terminal;

a second switch circuit having a plurality of analog switches for respectively coupling said outputs of said voltage dividing network to a second output terminal; and

analog switch control circuit means responsive to the pilot signal for scanning said analog switches of said first and second switch circuit such that said analog switches of each of said first and second switch circuits are sequentially enabled in a reciprocating manner over one cycle period of said subcarrier and a switch scan cycle of said first switch circuit is 180°

out of phase with that of said second switch circuit.