Data sense apparatus for use in multi-threshold read only memory

• US 4,404,655 A
• Filed: 01/28/1981
• Issued: 09/13/1983
• Est. Priority Date: 01/28/1981
• Status: Expired due to Term

• Current Assignee: General Instrument Corporation (CommScope Holding Company, Inc.)
• Original Assignee: General Instrument Corporation (CommScope Holding Company, Inc.)
• Inventors: Naiff, Kenneth L.
• Primary Examiner(s): Stellar, George G.
• Application Number:
  US06/229,717
• Time in Patent Office: 958 Days
• Field of Search: 365/103, 365/104, 365/105, 365/168, 365/45
• US Class Current: 365/104
• CPC Class Codes: G11C 11/5642 Sensing or reading circuits; Data output circuits
• CPC Class Codes: G11C 11/5692 read-only digital stores using storage elements with more than two stable states
• CPC Class Codes: G11C 17/12 using field-effect devices

Abstract

A read only memory in which the memory cells are single metal gate or silicon gate field effect transistors. Each FET has one of several different thresholds or states. The size or area of the FET gates at the surface of the semiconductor chip are substantially the same regardless of the cells threshold or state. The input to the gates is a ramp, and the cells are rendered conducting by the amplitude of the ramp at a given instant. The output of a cell is fed to several flip-flops, which are synchronized with the input ramp, thereby setting the flip-flops in accordance with the threshold or state of the cell. An encoder converts the output from the flip-flops to a bit binary signal. This permits a very high density ROM, e.g. 128K on a single chip. In another embodiment the input to the gates is a step, and the cells are all rendered conducting simultaneously. The amount of current drawn by each gate however, depends upon the doping in the gate region. The amplitude of the current being drawn by a selected cell is compared with the reference , this in turn is decoded to indicate the state of that cell.

Claims

1. A read only memory comprising a plurality of multi-state cells interconnected in a ROM matrix, each of said cells comprising a FET, and the FET of each ROM cell having substantially the same surface area and shape, and having one of at least three possible states;

means for selecting a particular one of said cells to be read;

means for applying to a selected cell, an input signal varying in amplitude with time for stimulating an output signal from said cell in accordance with the state of said cell, said output signal being of one at least two possible amplitude levels;

said input signal varies slowly with time, and said output signal being displaced in time depending upon the state of said cell.

2. A read only memory according to claim 1 wherein each cell has one of at least four states;

three of said states are gate threshold levels responsive to different amplitudes of said input signal, and the fourth state is not operable by said input signal;

said cell being switches at a different instant of time during the application of said input signal if in one of said first three states, and not being switched at all by said applied input signal if having said fourth state.

3. A read only memory according to claim 2 wherein the FET structure has a gate region having different degrees of doping corresponding to said three different states.

4. A read only memory according to claim 1,

wherein one of said states causes said cell to remain unchanged during reading, and said output signal from said cells in said one state being of one amplitude level;

and the output signals from said cells in the other states being the other amplitude level and displaced in time in accordance with their state.

5. A read only memory according to claim 4, further comprising at least three reference circuits connected to receive said input signal, each of said circuits having a cell in different one of said other states, and providing said time displaced output signal of said other amplitude in accordance with the state of said circuits;

at least three flip-flops each having two inputs and an output, said first inputs being connected to the output of said at least three reference circuits respectively, and the second inputs being connected to receive the output of the cell being read;

each of said flip-flops providing an output signal in accordance with coincidence of signals at its two inputs.

6. A read only memory in accordance with claim 5 further comprising an encoder connected to receive the output from the three flip-flops and providing a two bit binary signal in accordance with the output from the flip-flops.

7. A read only memory according to claim 5 further comprising a delay circuit between at least one of said reference circuits and the input to its corresponding flip-flop.

8. A read only memory according to claim 5, wherein said referenced circuits comprise three cells having FETs with substantially the same surface dimension as the cells in the ROM matrix.

9. A read only memory according to claim 5, wherein said multistate cells in the ROM matrix each comprise a FET having a gate region with different gate doping corresponding to said three threshold levels, and said three reference circuits each comprise a FET, at least one of which has one of said different gate doping of said matrix FETs, and a substantially different gate surface dimension than the corresponding FET cell in the matrix.

10. A read only memory according to claim 9, wherein at least two of said three reference circuits have FETs with surface gate dimensions different from those of the FETs in said matrix.

11. A read only memory in accordance with claim 10, wherein one of said reference cells FET is an enhancement mode, and with the same gate dimension as the FETs in the matrix;

said second reference circuit FET being of the enhancement mode and with larger surface gate region, and said third reference circuit FET being of the intermediate threshold level and having a larger surface gate region.