Semiconductor memory circuit
First Claim
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1. A semiconductor memory circuit of the MOSRAM type comprising:
- a plurality of bit lines;
a sense amplifier provided for each bit line for sensing a state of a storage cell selectively coupled to said bit line and for setting said bit line to one of first and second predetermined potentials in response to the sensed state;
a potential decision circuit provided for each bit line for sensing the potential on the corresponding bit line set by said sense amplifier; and
a boost circuit operating in response to an output from said potential decision circuit for increasing a potential on the corresponding bit line above a maximum supply potential when said potential decision circuit senses the presence of a predetermined one of said first and second potentials on said bit line for recharging said selected storage cell at a potential above said maximum supply potential.
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Abstract
A MOSRAM type semiconductor memory circuit in which the storage charge per bit cell is increased without a corresponding increase in per bit chip area. A potential decision circuit is provided for each bit line in the memory for setting a potential on the corresponding bit line. A boost circuit is provided for increasing the potential on each bit line in accordance with the operation of the potential decision circuit. One boost circuit may be provided for each bit line. Alternatively, a boost circuit may be provided common to all bit lines or a plurality of bit lines in the memory circuit.
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Citations
5 Claims
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1. A semiconductor memory circuit of the MOSRAM type comprising:
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a plurality of bit lines; a sense amplifier provided for each bit line for sensing a state of a storage cell selectively coupled to said bit line and for setting said bit line to one of first and second predetermined potentials in response to the sensed state; a potential decision circuit provided for each bit line for sensing the potential on the corresponding bit line set by said sense amplifier; and a boost circuit operating in response to an output from said potential decision circuit for increasing a potential on the corresponding bit line above a maximum supply potential when said potential decision circuit senses the presence of a predetermined one of said first and second potentials on said bit line for recharging said selected storage cell at a potential above said maximum supply potential. - View Dependent Claims (2, 3, 4, 5)
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Specification