Matrix screening and grounding arrangement and method

• US 4,405,917 A
• Filed: 04/28/1981
• Issued: 09/20/1983
• Est. Priority Date: 04/28/1981
• Status: Expired due to Term

• Current Assignee: Key Tronic Corporation, Inc.
• Original Assignee: Honeywell Incorporated (Honeywell International Inc.)
• Inventors: Chai, Thomas Y.
• Primary Examiner(s): Groody, James J.
• Application Number:
  US06/258,248
• Time in Patent Office: 875 Days
• Field of Search: 340/365 R, 340/365 S, 340/365 E, 340/365 C, 178/17 C, 178/17 A
• US Class Current: 341/26
• CPC Class Codes: G06F 3/044 by capacitive means
• CPC Class Codes: G06F 3/0446 using a grid-like structure of electrodes in at least two directions, e.g. using row and column electrodes

Abstract

A capacitance keyboard matrix screening and grounding arrangement and method are disclosed in which scanning drive means and scanning sense means sequentially address drive and sense conductors in drive and sense conductor arrays respectively and maintain a reference potential on all conductors except for individual conductors while they are being addressed. The scanning drive and sense means are implemented with demultiplexers whose output terminals are each connected to a drive or sense conductor through an inverter.

Claims

1. Capacitive keyboard apparatus comprising:

a matrix of capacitive key switches having first and second sets of conductors and a plurality of capacitors, each capacitor having fixed and movable plates, the fixed plates being connected to the first set of conductors and the movable plates being connected to the second set of conductors so that each capacitor is connected to a unique pair of conductors comprising one conductor from each of the first and second sets of conductors;

scanning drive means for sequentially supplying a drive signal to individual conductors of one of the first and second sets of conductors while maintaining all other conductors of the set at a reference potential;

a first digital demultiplexer having a plurality of output terminals which are normally at a logical high state and are selectively caused to go to a logical low state in response to an address signal supplied to address signal means thereon;

a plurality of inverters, each connecting an output terminal of said first digital demultiplexer to a separate conductor of the other of the first and second sets of conductors, whereby individual conductors of said other set are normally at the reference potential, and are selectively permitted to go to a different potential to permit sensing of capacitive coupling with conductors of said one of the first and second sets;

an analogue multiplexer having a plurality of input terminals each connected to a separate conductor in the set of conductors on which capacitive coupling is sensed, said analogue multiplexer being operable to transfer the signal from a selected conductor to an output terminal in response to an address signal supplied to address signal means; and

an address generator for supplying coordinated address signals to said first digital demultiplexer and said analogue multiplexer so that the conductor permitted to assume a potential different from the reference potential is the conductor whose signal is transferred by said analogue multiplexer, thereby precluding any transfer of signals between conductors other than the conductor receiving the drive signal and the conductor on which capacitive coupling is sensed.

2. The capacitive keyboard apparatus of claim 1 wherein said scanning drive means comprises:

bias means tending to maintain individual conductors of the set of conductors to which drive signals are supplied at a potential higher than the reference potential;

a second digital demultiplexer having a plurality of output terminals which are normally at a logical high state and may be selectively caused to go to a logical low state by address signals supplied to address terminal means thereon; and

which

a plurality of inverters, each connecting an output terminal of said second digital demultiplexer to a separate conductor of the set of conductors to which drive signals are supplied, whereby the conductors are normally maintained at the reference potential, and are sequentially caused to go to the potential determined by said bias means.

3. In combination:

an array of key actuable variable capacitors, each having first and second plates;

a first plurality of electrical conductors, each connected to the first plates of a separate row of said capacitors;

a second plurality of electrical conductors, each connected to the second plates of a separate column of said capacitors;

sensing means for sequentially addressing individual conductors in one of said first and second pluralities of electrical conductors to receive signals therefrom;

a first digital demultiplexer having a plurality of output terminals which are normally at a logical high state and which can be selectively caused to go to a logical low state in response to an address signal supplied to address terminal means thereon;

means for supplying address signals to said first digital demultiplexer to cause the output terminals thereof to sequentially go to a logical low state;

a first plurality of inverters, each connecting one output terminal of said first digital demultiplexer to one of the conductors in the other of said first and second pluralities of electrical conductors; and

bias means tending to maintain the conductors in the plurality of electrical conductors addressed by said first digital demultiplexer at a potential higher than a reference potential, whereby the conductors are normally maintained at the reference potential and whereby the higher potential is selectively impressed on individual conductors.

4. The combination of claim 3 wherein said sensing means comprises:

an analogue multiplexer having a plurality of input terminals, each input terminal being connected to a separate conductor in the plurality of electrical conductors addressed by said sensing means, said analogue multiplexer being operable to transfer the signal from a selected conductor to a detector output terminal in response to an address supplied to address terminal means;

a second digital demultiplexer having a plurality of output terminals which are normally at a logical high state and can be selectively caused to go to a logical low state in response to a signal supplied to address terminal means thereon;

a second plurality of inverters, each connecting an output terminal of said second digital demultiplexer to one of the conductors in the plurality of electrical conductors addressed by said sensing means, whereby the conductors are normally maintained at the reference potential and whereby individual conductors are selectively permitted to assume a potential other than the reference potential; and

means connecting the address terminal means of said analogue multiplexer and said second digital demultiplexer so that they substantially simultaneously address the same conductor.

5. The combination of claim 4 wherein said reference potential is electrical ground.

6. In a capacitive keyboard apparatus of the type in which first and second sets of conductors are coupled by an array of key actuated variable capacitors such that each capacitors couples a different pair of conductors comprising one conductor from each set, and the sets of conductors are scanned to detect actuated capacitors, improved screening apparatus which comprises:

a first digital demultiplexer having a plurality of output terminals which are normally at a logical high state and which can be selectively caused to go to a logical low state in response to an address signal supplied to address terminal means thereon;

a plurality of inverters, each connecting one output terminal of said digital demultiplexer to a separate conductor in the first set of conductors, whereby the conductors in the first set of conductors are normally maintained at a reference potential and are sequentially permitted to assume a potential different from the reference potential;

a scanning detector for sequentially sensing the potentials on individual conductors in the first set of conductors; and

control means for providing coordinated operation of said first digital demultiplexer and said scanning detector so that said scanning detector senses the potential on each conductor in the first set of conductors only during the time interval in which the conductor is permitted to assume a potential different from the reference potential.

7. The capacitive keyboard apparatus of claim 6 further comprising:

a second digital demultiplexer having a plurality of output terminals which are normally at a logical high state and which can be selectively caused to go to a logical low state in response to an address signal supplied to address terminal means thereon;

a plurality of inverters, each connecting one output terminal of said digital demultiplexer to a separate conductor in the second set of conductors; and

bias means tending to maintain the conductors in the second set of conductors at a potential different from the reference potential, whereby the conductors in the second set of conductors are normally maintained at the reference potential and are sequentially impressed with a potential different from the reference potential.

9. The capacitive keyboard apparatus of claim 7 wherein said scanning drive means comprises:

a second digital demultiplexer having address terminal means and a plurality of output terminals, said second demultiplexer providing a logical high state at its output terminals except for any output terminal during the time it is addressed by an address signal supplied to the address terminal means; and

a second plurality of inverters, each connecting an output terminal of said second digital demultiplexer to a separate conductor of said second plurality of conductors, whereby the conductors of said second plurality of conductors, except for the conductor associated with the addressed output terminal, are maintained at the reference potential.

8. Capacitive keyboard apparatus comprising:

a first plurality of electrical conductors;

a second plurality of electrical conductors;

an array of key actuable variable capacitors;

means for interconnecting said capacitors and said first and second pluralities of conductors such that each capacitor is connected between a different pair of conductors comprising one conductor from said first plurality of conductors and one conductor from said second plurality of conductors, whereby variable capacitive coupling is provided between conductors in a pair, the magnitude of the capacitive coupling being dependent on the state of actuation of the associated capacitor;

a first digital demultiplexer having address terminal means and a plurality of output terminals, said first demultiplexer providing a logical high state at its output terminals except for any output terminal during the time it is addressed by an address signal supplied to the address terminal means;

a first plurality of inverters, each connecting an output terminal of said first digital demultiplexer to a separate conductor of said first plurality of conductors, whereby the conductors of said first plurality of conductors, except for the conductor associated with the addressed output terminal, are maintained at a reference potential;

an analogue multiplexer having a plurality of input terminals each connected to a separate conductor of said first plurality of conductors, an output terminal and address terminal means, said multiplexer being operable to transfer the signal from any selected input terminal to its output terminal in response to an address signal supplied to the address terminal means;

a scanning address generator for supplying address signals which cause said analogue multiplexer to transfer signals only from the conductor associated with the addressed output terminal of said first digital demultiplexer; and

scanning drive means for supplying a drive potential to individual conductors of said second plurality of conductors in sequence and maintaining all conductors of said second plurality conductors except the conductor to which the drive potential is supplied at a reference potential.