FET Circuit for converting TTL to FET logic levels

• US 4,406,956 A
• Filed: 08/11/1980
• Issued: 09/27/1983
• Est. Priority Date: 09/01/1979
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Clemen, Rainer, Fischer, Walter, Haug, Werner O.
• Primary Examiner(s): Zazworsky, John
• Application Number:
  US06/177,298
• Time in Patent Office: 1,142 Days
• Field of Search: 307/264, 307/448, 307/475, 307/482, 307/578
• US Class Current: 326/70
• CPC Class Codes: H03K 19/018507 Interface arrangements

Abstract

This invention relates to a field effect transistor level converter for converting bipolar transistor logic levels to field effect transistor logic levels. First and second field effect transistors have their source and gate electrodes connected in common. The bipolar input signal is received at the common source connection while the gate electrodes receive a fixed reference potential that is equal to the threshold voltage VT plus the lowest possible high binary level of the bipolar input logic. The drain electrode of the first field effect transistor is connected to the output terminal of the level converter and the source electrode of a source follower transistor. The drain electrode of the second transistor is connected to a load device and to the gate of the source follower transistor which has its drain electrode connected to VH. This arrangement produces at the first output terminal a potential swing of approximately 0 to 7 volts in response to an input signal in the range of 0.8 to 2.0 volts.

Claims

1. A field effect transistor circuit for converting bipolar transistor logic levels to field effect transistor logic levels independent of field effect transistor threshold voltage variations, comprising:

first and second field effect transistors each having a gating electrode and first and second gated electrodes and having their respective gating electrodes and first gated electrodes connected in common;

means for biasing said gating electrodes of said first and second transistors connected in common to a reference potential;

an input terminal connected to said first gated electrodes of said first and second field effect transistors connected in common;

the second gated electrode of said first field effect transistor being connected to an output terminal and to a first gated electrode of a third field effect transistor;

the second gated electrode of said second field effect transistor being connected to a load device and to a gating electrode of said third field effect transistor;

a second gated electrode of said third field effect transistor and said load device being connected to a first potential source; and

a fourth field effect transistor having a gating electrode and first and second gated electrodes, the second gated electrode of said fourth field effect transistor being connected to said output terminal, the first gated electrode of said fourth field effect transistor being connected to a second potential source, and the gating electrode of said fourth field effect transistor being connected to an output of a power inverting circuit having its input coupled to said output terminal.

2. A field effect transistor circuit as in claim 1 wherein said power inverting circuit comprises:

a field effect transistor power inverting circuit having an input and at least two outputs, with said input being directly connected to said output terminal and with one of said at least two outputs being directly connected to the said gating electrode of said fourth field transistor, said last mentioned connection forming a positive feedback path.

3. A field effect transistor circuit as in claim 1 wherein said means for biasing the common gating electrode to a reference potential biases the common gating electrode to a potential level substantially equal to the sum of logical up level signals applied at the input terminal plus the threshold voltage of said first and second field effect transistors.

4. A field effect transistor circuit as in claim 1 wherein said load device comprises:

a fifth field effect transistor connected in a series electrical path between said first potential source and the common connection of the second gated electrode of said second field effect transistor and the gating electrode of said third field effect transistor;

a bootstrap capacitor electrically coupling the gate and source electrodes of said fifth field effect transistor; and

a diode connected field effect transistor connected in a series electrical path between said first potential source and the gate electrode of said fifth field effect transistor.

5. A field effect transistor logic circuit for converting first binary logic levels to second binary logic levels comprising:

a plurality of field effect transistors each having a gating electrode, a source electrode, and a drain electrode, formed on an integrated circuit chip and having substantially the same threshold voltage;

first and second of said plurality of field effect transistors being connected in a series electrical path between first and second sources of potential, the source electrode of said first field effect transistor being connected to the drain electrode of said second field effect transistor and forming a common circuit point;

an input terminal adapted to receive logic signals at said first binary logic levels;

third of said plurality of field effect transistors connected in a series electrical path between said input terminal and the said gating electrode of said first field effect transistor;

fourth of said plurality of field effect transistors connected in a series electrical path between said input terminal and said common circuit point forming a direct current connection between said input terminal and said common circuit point when said fourth of said plurality of field effect transistors is in its conductive state;

a bias signal potential connected to the gating electrodes of both said third and fourth field effect transistors for applying a bias potential substantially equal to the sum of the logical level signal applied at said input terminal and the said threshold voltage of said field effect transistors;

a load connected between said first source of potential and the gating electrode of said first field effect transistor and

circuit means formed of additional field effect transistors of said plurality of field effect transistors having an input connected to said common circuit point and an output connected to the gating electrode of said second field effect transistor.

6. A field effect transistor logic circuit as in claim 5 wherein said load comprises:

a bootstrapped field effect transistor.

7. A field effect transistor logic circuit as in claim 5 wherein said additional field effect transistors comprise:

a field effect transistor inverting circuit forming a positive feedback path.