Column and row erasable EEPROM
First Claim
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1. An electrically erasable programmable read only memory (EEPROM) comprising:
- an array of electrically erasable memory elements arranged with one of said memory elements at the intersection of each of a plurality of rows and columns of said array;
logic means for generating, in response to a row erase mode signal, a row control signal at a first logic state and a column control signal at a second logic state;
column select means for coupling, when the column control signal is at the second logic state, an erase signal to all of the columns of said array; and
row decoder means for enabling, when the row control signal is at the first logic state, said erase signal to electrically erase the memory elements comprising the row of said array selected in response to a row address signal.
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Abstract
An EEPROM has an array of memory elements arranged by row and column which is accessed by a decoder capable of selecting all columns while enabling a single row in response to one input and selecting one column while enabling all rows in response to another input, thereby selectively erasing one entire row or column.
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4 Claims
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1. An electrically erasable programmable read only memory (EEPROM) comprising:
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an array of electrically erasable memory elements arranged with one of said memory elements at the intersection of each of a plurality of rows and columns of said array; logic means for generating, in response to a row erase mode signal, a row control signal at a first logic state and a column control signal at a second logic state; column select means for coupling, when the column control signal is at the second logic state, an erase signal to all of the columns of said array; and row decoder means for enabling, when the row control signal is at the first logic state, said erase signal to electrically erase the memory elements comprising the row of said array selected in response to a row address signal. - View Dependent Claims (2)
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3. An electrically erasable programmable read only memory (EEPROM) comprising:
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an array of electrically erasable memory elements arranged with one of said memory elements at the intersection of each of a plurality of rows and columns of said array; logic means for generating in response to a column erase mode signal a column control signal at a first logic state and a row control signal at a second logic state; row select means for coupling, when the row control signal is at the second logic state, an erase signal to all of the rows of said array; and column decoder means for enabling, when the column control signal is at the first logic state, said erase signal to electrically erase the memory elements comprising the column of said array selected in response to a column address signal. - View Dependent Claims (4)
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Specification