Processor facilities for integrated packet and voice switching

• US 4,408,323 A
• Filed: 06/29/1981
• Issued: 10/04/1983
• Est. Priority Date: 06/29/1981
• Status: Expired due to Term

• Current Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Original Assignee: Bell Telephone Laboratories, Inc. (Nokia Corporation)
• Inventors: Montgomery, Warren A.
• Primary Examiner(s): Olms, Douglas W.
• Application Number:
  US06/278,861
• Time in Patent Office: 827 Days
• Field of Search: 370/60, 370/58, 370/94, 370/66
• US Class Current: 370/389
• CPC Class Codes: H04L 12/64 Hybrid switching systems
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04M 11/06 Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors

Abstract

A communication method and switching system in which voice and data signals are communicated through the system by a programmed controlled switching processor. The switching processor reads these signals from an input memory where they were transferred from telephone stations and data terminals by a scanner. The voice and data signals are transmitted to telephone stations and data terminals by the switching processor storing these signals in an output memory from which they are retransmitted by a distributor to the telephone stations and data terminals. The intelligent processor reads data signals from the input memory and assembles these signals into data packets which are temporarily stored in the data memory. Subsequently, the intelligent processor transmits these data packets by storing the data signals in the output memory. The intelligent processor is controlled by program instructions from its program memory and data stored in a data memory by a parameter processor which has associated program and data memories.

Claims

1. A telecommunication switching system for interconnecting digitally encoded voice signals between a set of randomly selectable input ports and a set of randomly selectable output ports and for assembling digital data signals from another set of said randomly selectable input ports into packets and transmitting said packets to another set of said randomly selectable output ports, said system comprising:

a first storage means for storing said digitally encoded voice signals and said digital data signals from said input ports into predetermined storage locations;

switching processor means responsive to a receipt of a first set of program instruction routines for processing said stored digitally encoded voice signals;

a second storage means connectable to said output ports for storing said processed voice signals in predetermined storage locations thereof;

said switching processor means being responsive to a receipt of a second set of program instruction routines for processing said stored digital data signals to assemble and store said packets in said switching processor means; and

said switching processor means being responsive to a receipt of a third set of program instruction routines for processing each of said packets for transmission of each of said processed packets to said second storage means;

whereby said stored packets are transmitted to said other set of said output ports.

2. The invention of claim 1 wherein said switching processor means comprises a first processor means, a first memory means, and a second memory means having a first memory buffer containing a plurality of memory locations and a second memory buffer containing a plurality of memory locations;

said first memory means having a plurality of word locations for storing instruction signals representing said second set of program instruction routines and said first memory means repetitively accessed to transmit said instruction signals to said first processor means;

said first processor means responsive to said instruction signals for reading a first digital word of digital data signals from a storage location in said first storage means associated with a designated one of said other set of said input ports and for storing the read first digital word in one of said memory locations of said first memory buffer reserved for the assembly of a packet of said digital data words for said designated one of said other set of said input ports.

3. The invention of claim 2 wherein said first processor means is responsive to said instruction signals and a second digital word stored in a second memory location of said second memory means to affect said reading of said first digital word from said first storage means.

4. The invention of claim 3 wherein said switching processor means further comprises a second processor means, a third memory means, and a fourth memory means;

said third memory means comprises a first memory segment associated with said second digital word of said second memory means, and said first memory segment of said third memory comprises a plurality of memory locations;

said fourth memory means having a plurality of memory locations for storing instruction signals, and said fourth memory means repetitively accessed to transmit all of said fourth memory means instruction signals to said second processor means within a fixed time period; and

said second processor means responsive to said instruction signals to said fourth memory means for reading one digital word from said first memory segment of said third memory means and for storing said read digital word from said first memory segment in said second memory location of said second memory means.

5. The invention of claim 3 wherein said first processor means is responsive to said instruction signals and a third digital word stored in a third memory location of said second memory means for said storing of the read first digital word in said one of said memory locations of said first memory buffer associated with said designated one of said other set of said input ports.

6. The invention of claim 5 wherein said switching processor means further comprises a second processor means, a third memory means, and a fourth memory means;

said third memory means comprises a second memory segment associated with said third digital word of said second memory means, and said second memory segment of said third memory having a plurality of memory word locations;

said fourth memory means having a plurality of memory locations for storing instruction signals, and said fourth memory means repetitively accessed to transmit all of said fourth memory means instruction signals to said second processor means within a fixed time period; and

said second processor means is responsive to said instruction signals of said fourth memory means for reading one digital word from said second memory segment of said third memory means and for storing said read digital word from said second memory segment in said third memory location of said second memory means.

7. The invention of claim 2 wherein said first memory means further stores other instruction signals representing said third set of program instruction routines and said first memory means repetitively accessed to transmit said other instruction signals to said first processor means;

said first processor means is responsive to said other instruction signals for reading a second digital word stored in a second memory location of said second memory buffer in said second memory means which is reserved for a completed packet of digital words awaiting transmission to a designated one of said other set of said output ports and for storing said read second digital word in a memory location of said second storage means associated with said designated one of said other set of said output ports.

8. The invention of claim 7 wherein said first processor means is responsive to said other instruction signals and a third digital word stored in a third memory location of said second memory means for said reading of the second digital word from said second memory location.

9. The invention of claim 8 wherein said switching processor means further comprises a second processor means, a third memory means, and a fourth memory means;

said third memory means comprises a first memory segment associated with said third digital word of said second memory means, and said first memory segment of said third memory comprises a plurality of memory word locations;

said fourth memory means having a plurality of memory locations for storing instruction signals, and said fourth memory means repetitively accessed to transmit all of said fourth memory means instruction signals to said second processor means within a fixed time period; and

said second processor means responsive to said instruction signals of said fourth memory means for reading one digital word from said first memory segment of said third memory means and for storing said read digital word for said first memory segment in said third memory location of said second memory means.

10. The invention of claim 8 wherein said first processor means is responsive to said other instruction signals and a fourth word stored in a fourth memory location of said second memory means for said storing of the read second digital word in said storage location of said second storage means associated with said designated one of said other set of said output ports.

11. The invention of claim 10 wherein said switching processor means further comprises a second processor means, a third memory means, and a fourth memory means;

said third memory means comprises a first memory segment associated with said fourth digital word of said second memory means, and said first memory segment of said third memory comprises a plurality of memory word locations;

said fourth memory means having a plurality of memory locations for storing instruction signals, and said fourth memory means repetitively accessed to transmit all of said fourth memory means instruction signals to said second processor means within a fixed time period; and

said second processor means is responsive to said instruction signals of said fourth memory means for reading one digital word from said first memory segment of said third memory means and for storing said read digital word from said first memory segment in said fourth memory location of said second memory means.

13. The invention of claim 11, wherein said second processor is responsive to said receipt of said instructions from said second program memory for reading the contents of a second memory location of said data memory and for storing said read contents of said second memory location in a third memory location of said first data memory;

said first processor is responsive to said receipt of said instructions from said first program memory and said contents of said third memory location to read a first word of digital data from said first storage means.

14. The invention of claim 13, wherein said second processor responsive to said instructions from said second program memory to read contents of a fourth memory location in said second data memory and for storing said contents of said fourth memory location in a fifth memory location of said first data memory;

said first processor is responsive to said instructions from said first program memory and said contents of said fifth memory location for storing said first word in said first data memory as part of a packet associated with said destination one of said output terminals.

12. A telecommunication switching system for the integrated switching of voice telephone calls and the assembly and switching of data packets, said system comprising:

a plurality of telephone stations and data terminals;

a first storage means for storing digital encoded voice signals from said telephone stations and digital data signals from said data terminals into predetermined storage locations;

a second storage means for storing said digitally encoded voice and digital data signals into predetermined storage locations for transmission to said telephone stations and said data terminals;

apparatus for switching said encoded voice signals and digital data signals from said telephone stations and data terminals, respectively, and storing said encoded voice and digital data signals in said memory locations of said first storage means, and to transfer said encoded voice and digital data signals from said second storage means to said telephone stations and data terminals, respectively;

a switching processor responsive to a receipt of program instructions for controlling the switching of said voice and digital data signals from said first storage means to said second storage means and communication therefrom to said stations and said terminals;

said switching processor having a first processor and a first program memory for supplying said program instructions to said first processor, a first data memory, a second processor responsive to a receipt of instructions from a second program memory, and a second data memory for supplying data to said second processor;

said first memory cooperative with said second processor for controlling operation of said first processor;

said second data memory having a plurality of memory locations cooperative with said first and second processors for assembling packets of data read from said first storage means in said first data memory via said first processor, and for transferring assembled data packets from said first data memory to said second storage means for transmission to a destination in one of said terminals via said apparatus.

15. The invention of claim 12, wherein said second processor is responsive to a receipt of one of said instructions from said second program memory for reading the contents of a sixth memory location in said second data memory for storing the read contents of said sixth memory location in a seventh memory location in said first data memory;

said first processor is responsive to said receipt of said instructions from said first program memory and said contents of said seventh memory location for reading word from said packet associated with said destination one of said data terminals stored in said first data memory.

16. The invention of claim 15, wherein said second processor is responsive to a receipt of another one of said instruction from said second program memory to read contents of an eight memory location stored in said second data memory and for storing said contents of said eighth memory location in a ninth memory location of said first data memory;

said first processor is responsive to said receipt of said instructions from said first program memory and said contents of said ninth memory memory location for storing said word from said packet in the word of said output memory associated with said destination one of said data terminals.

17. For use in a communication switching system for integrated voice and data services and comprises:

a plurality of telephone stations and data terminals;

a first storage means for storing digitally encoded voice signals from said telephone stations and digital signals from said data terminals into predetermined storage locations;

a second storage means for storing processed digitally encoded voice and digital data signals into predetermined storage locations for transmission to said telephone station and said data terminals;

apparatus for switching said encoded voice signals and digital data signals from said telephone stations and data terminals, respectively, and storing said encoded voice and digital data signals in said memory locations of said first storage means and to transfer said encoded voice and digital data signals from said second storage means to said telephone stations and data terminals;

a switching processor responsive to receipt of stored program instructions to communicate encoded voice signals from calling ones of said stations stored in said first storage means to said second storage means for subsequent communication through said apparatus to called ones of said telephone stations;

said switching processor having a first processor and a first program memory for supplying said first processor with said program instructions, a first data memory, a second processor responsive to instructions from a second program memory, and a second data memory for supplying data to said second processor;

the invention comprises means in said first processor responsive to instructions from said first program memory and data transmitted from said second processor via said first data memory for assembling packets of data read from said first storage means in said first data memory and for transferring assembled data packets from said first data memory to said second storage means for transmission to a destination one of said terminals via said apparatus;

said second processor responsive to said instructions from said second program memory to read data from said second data memory and store said data in said first data memory.

18. A method for communicating voice signals between telephone stations and for assembling data signals from data terminals into data packets and for transmission of assembled data packets to destination data terminals;

communicating said voice and data signals from one of said telephone stations and one of data terminals, respectively, for storage in an input memory;

sending the voice signals from said input memory for storage in an output memory;

communicating the voice signals from said output memory to one of said telephone stations;

transferring the data signals from said input memory for storage in a buffer in a data memory associated with a destination one of said data terminals until said buffer contains a completed packet;

communicating the data signals from said buffer containing said completed packet for storage in said output memory;

sending the data signals from said output memory to said destination one of said data terminals.

19. The invention of claim 18 wherein said transferring step is characterized by assigning said buffer from a group of unassigned buffers upon receiving the first digital word of said packet from said input memory at the start of transmission of said packet.

20. The invention of claim 19 wherein said buffer of said group of unassigned buffers is identified by contents of a first memory location in said data memory and contents of the first memory location of said buffer identifying another one of said unassigned buffers and characterized by

transferring said contents of said first memory location in said data memory to a second memory location in said data memory associated with said one of data terminals for assigning said buffer to said destination one of said data terminals;

transferring said contents of said first memory location of said buffer to said first memory location in said data memory for identifying said other one of said unassigned buffers by said contents of said first memory location in said data memory.

21. The invention of claim 18 wherein the digital word of said packet of said data signals designating a number of words in said packet and being stored in a first memory location of said data memory.

22. The invention of claim 21 further comprising the step of identifying said first memory location by

accessing the contents of a second memory location of said data memory for obtaining the address of said first memory location, and

storing the first word of said packet in said first memory location under address control of said contents of said second memory location.

23. The invention of claim 22 comprising the step of storing the contents of a third memory location in a parameter memory into said second memory location by

reading said contents of said third memory location from said parameter memory, and

storing said read contents of said third memory location in said second memory location of said data memory.

24. The invention of claim 18 wherein said step of transferring said data signals from said input memory to said buffer in said data memory is characterized by identifying the memory location of a digital word containing said data signals and associated with said one of said data terminals in said input memory by

accessing contents of a first memory location in said data memory to obtain the address identifying said memory location of said digital word associated with said one of said data terminals, and

addressing said memory location in said input memory with said contents of said first memory location, and reading said associated digital word from said input memory for transferring said associated digital word to said buffer in said data memory.

25. The invention of claim 24 further comprising the step of transferring the contents of a second memory location in a parameter memory into said first memory location by

reading said contents of said second memory location from said parameter memory, and

storing said contents of said second memory location in said first memory location of said data memory whereby said contents of said second memory location controls the identification of said associated digital word in said input memory.

26. The invention of claim 21 further comprising the step of detecting the completed assembly of said data packet by

initializing a second digital word stored in a second memory location of said data memory to a preset value,

incrementing said contents of said second memory location upon receipt of each data word from said one of said data terminals for accumulating in said second memory location the number of received data packet words,

comparing the contents of said second memory location with the contents of said first memory location for checking whether said number of received packet words equals the expected number of packet words with a match indicating completion of said packet.

27. The invention of claim 26 further comprising the step of identifying said second memory location in said data memory by

accessing the contents of a third memory location of said data memory for obtaining the address of said second memory location, and

reading said contents of said second memory location under address control of said read contents of said third memory location.

28. The invention of claim 27 further comprising the step of transferring the contents of a fourth memory location of a parameter memory into said third memory location for controlling the addressing of said second memory location by

reading said contents of said fourth memory location from said parameter memory, and

storing said read contents of said fourth memory location in said third memory location of said data memory.

29. The invention of claim 20 further comprising the step of identifying the memory location in said buffer for storing a data word of said data signals from said one of said data terminal by

identifying the first word of said buffer by storing the address of said first word of said buffer in said second memory location;

initializing the contents of a third memory location of said data memory to a preset value;

incrementing said contents of said third memory location upon receipt of each digital word of data signals from said one of said data terminals for accumulating in said third memory location the number of received data packet words;

adding said contents of said second memory location to contents of said third memory location for identifying said memory location in said buffer;

storing said digital word in said memory location in said buffer identified by results of said addition.

30. The invention of claim 29 further comprising the step of identifying said second memory location in said data memory by

reading the contents of a fourth memory location of said data memory;

and

reading said contents of said second memory location under address control of said read contents of said fourth memory location.

31. The invention of claim 30 further comprises the step of transferring the contents of a fifth memory location in a parameter memory into said fourth memory location for controlling the identification of said second memory location by said contents of said fifth memory location;

reading said contents of said fifth memory location from said parameter memory; and

storing said read contents of said fifth memory location in said fourth memory location of said data memory.

32. The invention of claim 18 wherein said step of communicating said data signals from said buffer containing completed packet to said output memory characterized by storing said data signals in a first memory location in said output memory associated with said one of said destination data terminals and identifying said first memory location by

accessing contents of a second memory location in said data memory for obtaining the address of said first memory location;

and

storing a digital word of said data signals from said completed packet in said first memory location of said output memory under address control of said read contents of said second memory location for transferring said data signals to said destination one of said data terminals.

33. The invention of claim 32 further comprising the step of transferring the contents of a third memory location in a parameter memory into said second memory location by

reading said contents of said third memory location from said parameter memory;

and

storing said read contents of said third memory location in said second memory location of said data memory whereby said contents of said third memory location control the identification of said first memory location.

34. The invention of claim 20 wherein said buffer holding the assembled completed packet is identified with another one of buffers containing packets awaiting transmission to said one of said destination data terminals and identifying said other one of said buffers with contents of a third memory location and a fourth memory location in said data memory by

storing said contents of said first memory location in said data memory in the first memory location of said other one of buffers awaiting transmission for identifying said buffer holding the assembled completed packet with said other one of said buffers;

and

transferring contents of said first memory location of said data memory to said fourth memory location of said data memory for identifying said buffer holding the assembled completed packet as the last buffer awaiting transmission to said destination one of said data terminals.

35. The invention of claim 34 further comprising the step of first transmitting said packet stored in said other buffer and then transmitting said packet stored in said buffer by

identifying the first memory location of said other buffer with said contents of said third memory location;

identifying the first memory location of said buffer with said contents of said fourth memory location;

counting the number of words transmitted from the buffer identified by said contents of said third memory location by storing the number of words transmitted in a fifth memory location of said data memory;

adding said contents of said third memory location and said contents of said fifth memory location together, reading the next word to be transmitted from said other buffer under address control of the result of said addition and incrementing said contents of said fifth memory location, storing the read next word in said output memory and continuing until all words of said other buffer have been transmitted,

storing said contents of said first memory location of said other buffer in said third memory location for identifying said buffer as buffer to be transmitted to said destination one of said data terminals;

transferring contents of the first memory location of said buffer to said fourth memory location;

setting said contents of said fifth memory location to a predetermined value;

adding said contents of said third memory location and said contents of said fifth memory location together, incrementing said contents of said fifth memory location, reading the next word to be transmitted of said buffer under address control of the result of said second addition, and storing the read next word in said output memory and continuing until all words of said buffer have been transmitted.

36. The invention of claim 35 comprising a further step of identifying said fourth memory location in said data memory using contents of a sixth memory location in said data memory by

storing contents of a seventh memory location from a parameter memory in said sixth memory location in said data memory whereby said contents of said seventh memory location control the identification of said third memory location;

reading said contents of said sixth memory location in said data memory; and

reading said contents of said third memory location under address control of said contents of said sixth memory location.

37. The invention of claim 35 further comprises the step of identifying said fourth memory location in said data memory using the contents of a sixth memory location of said data memory by

storing contents of a seventh memory location of a parameter memory in said sixth memory location in said data memory for controlling the addressing of said fourth memory location by said contents of said seventh memory location;

accessing said contents of said sixth memory location of said data memory for obtaining the address of said fourth memory location; and

reading said contents of said fourth memory location under address control of said contents of said sixth memory location.

38. The invention of claim 35 further comprising a step of identifying said fifth memory location in said data memory using the contents of a sixth memory location of said data memory by

storing contents of a seventh memory location of a parameter memory in said sixth memory location in said data memory for controlling the addressing of said fifth memory location by said contents of said seventh memory location;

reading said contents of said seventh memory location of said data memory; and

reading said contents of said fifth memory location under address control of said read contents of said seventh memory location.