Turn-off-processor between keystrokes

• US 4,409,665 A
• Filed: 12/26/1979
• Issued: 10/11/1983
• Est. Priority Date: 12/26/1979
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Tubbs, Graham S.
• Primary Examiner(s): Chin, Gary
• Application Number:
  US06/106,430
• Time in Patent Office: 1,385 Days
• Field of Search: 364/707, 364/200, 364/900, 340/365 R, 340/365 S
• US Class Current: 713/321
• CPC Class Codes: G06F 1/00 Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00 architectures of general purpose stored program computers G06F15/76
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3265 Power saving in display device
• CPC Class Codes: G06F 15/0216 Constructional details or arrangements
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A calculator having constant memory utilizing a classical CMOS metal gate process, a low power microcomputer with on-chip and external constant memory capability, and multiple partition power control of circuit groups. Incorporation of a first and second switched negative voltage and a non-switched negative voltage to the appropriate P (-) wells enables the power hungry clocked logic and the display interface and keystroke detect circuitry, to be turned off while power is maintained on the internal static RAM, and on the RAM write logic, digit latches, and R-lines which connect to both the internal and external RAM, or to selectively connect in combination the first and second switched voltages. In an alternate embodiment, a multiple oscillator, multiple partition system is controlled to provide an off-mode, display only mode (low frequency oscillator), a process only mode, and a display and process mode, thereby optimizing power dissipation to system requirements. In yet another embodiment, the clocked CMOS logic of the system is forced to a designer predefined output logic level in the inactive power down mode. Thus, semi-non-volatile memory (constant memory) capability, power down standby, and display only, capabilities may be achieved. Power consumption less than conventional CMOS is obtainable.

Claims

1. An electronic data processing system comprising:

(a) operator input means including means for generating an ON signal, an OFF signal and a plurality of operation signals; and

(b) integrated circuit means, connected to said operator input means, having a process only mode, a display only mode, a process and display mode and an off mode, said integrated circuit means including (i) controller means having means for selectively generating inactive first and second control outputs when said integrated circuit means is in the off mode, means for selectively generating an active first control output and an inactive second control output when said integrated circuit means is in the process only mode, means for selectively generating an inactive first control output and an active second control output when said integrated circuit means is in the display only mode and means for selectively generating active first and second control outputs when said integrated circuit means is in the process and display mode, and (ii) clock generator means, connected to said controller means, including first means for selectively generating first clock outputs in an active cycling state in response to said active first control output and in an inactive predefined steady state in response to said inactive first control output and second means for selectively generating second clock outputs in an active cycling state in response to said active second control output and in an inactive predefined steady state in response to the inactive second control output.

2. The electronic data processing system of claim 1 wherein the integrated circuit is further comprised of:

(a) processor means, connected to the first means, for selectively executing instruction sequences corresponding to the received operation signals in response to receiving the first clock outputs in the cycling state;

(b) display interface means, connected to the second means, for selectively providing outputs representative of the information to be displayed for connection to the display in response to receiving the second clock outputs in the cycling state.