FM-Digital converter

• US 4,409,984 A
• Filed: 02/25/1981
• Issued: 10/18/1983
• Est. Priority Date: 02/25/1981
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Dick, Joseph B.
• Primary Examiner(s): Kamm, William E.
• Application Number:
  US06/237,821
• Time in Patent Office: 965 Days
• Field of Search: 328/140, 328/141, 328/220 R, 340/347, 364/417, 128/630, 128/696, 128/697, 128/903, 128/904
• US Class Current: 600/509
• CPC Class Codes: A61B 5/0006 ECG or EEG signals
• CPC Class Codes: H03K 7/06 Frequency or rate modulation, i.e. PFM or PRM
• CPC Class Codes: H03M 1/60 with intermediate conversion to frequency of pulses

Abstract

A square pulse wave is frequency modulated (FM) by an input analog voltage that represents a physiological parameter such as an electrocardiograph waveform. A binary counter is initiated for counting a predetermined integral number, such as four, FM periods for each FM wave sampling interval. A counter/timer counts high rate clock pulses during the interval and stops when the predetermined number of FM periods is counted, thereby producing a count that is proportional to the time per FM period or cycle. The reciprocal of time is calculated to produce a digital number that is proportional to frequency and, hence, to the instant amplitude of the analog input voltage. The number constitutes address to a look-up table storing digital words that correspond in value to dc voltages.

Claims

1. A multiple channel system for converting successive samples of analog input voltages for each channel to binary digital representations of the samples, respectively, where said analog voltages are represented, respectively, by frequency modulated (FM) signal trains comprised of substantially square wave cycles, said system comprising:

a gate having input and output means, one of said FM trains being fed to the input means of the gate,

a binary counter having input and output means, the output means of the gate being coupled to the input means of the counter,

means for initializing the counter at the beginning of each in a succession of FM signal sampling intervals, said counter responding to initialization by enabling the gate to feed the FM signal to said input means of the counter, said counter being operative to count a predetermined number of FM cycles and to disable the gate simultaneously with said number being counted to thereby terminate the sampling intervals,

a clock pulse generator for generating a train of pulses at a frequency substantially higher than the FM signal frequency,

counter/timer means having input means for the train of clock pulses and having output means for the binary digital numbers representing the number of clock pulses counted during each sampling interval, said counter/timer means responding to occurrence of said binary counter initialization by simultaneously beginning to count clock pulses and responding to occurrence of said predetermined number of FM cycles having been counted by terminating clock pulse counting, the binary number representative of the number of clock pulses counted during said number of FM cycles corresponding to the FM frequency during said sampling interval,

means for converting the numbers corresponding to FM frequency to binary digital values corresponding to the amplitude of the aforesaid analog input voltage during each FM signal sample.

2. The system as in claim 1 wherein said means for converting the numbers comprises a look-up table having a plurality of addressable locations respectively storing digital data corresponding to analog dc voltage values, said look-up table having address input means and digital data output means,

said binary digital numbers corresponding to FM frequency constituting addresses to said look-up table digital data locations, input of an address to said table resulting in output of digital data corresponding to an analog voltage value.

3. The system in any of claims 1 or 2 wherein:

said binary counter is set to count four FM cycles per sample of the FM signal train and the frequency of the clock pulses counted by said counter/timer is about 1.33 MHz.

4. Means for converting a train of frequency modulated (FM) pulse signals, whose frequency variations are representative of variations in the magnitude of an electrocardiograph (ECG) analog voltage used to modulate the signals, to digital numbers corresponding in value to the magnitude of the analog voltage waveform prevailing at times the FM signals are sampled, comprising:

a gate having one input for said train of FM pulses, an input for a gating signal and an output for the FM pulse train,

a first edge triggered counter means having an input for the gated FM pulse train, one output coupled to said gating signal input and another output, said counter responding to being initialized by providing said gating signal and responding to counting a predetermined number of FM pulses by terminating said gating signal, said counter further responding to being triggered by an edge of the first FM pulse sample to be counted by setting said other output to one state and responding to the corresponding edge of the last FM in the sample by changing said output to another state,

second counter means having input means for a clock pulse train whose frequency is substantially higher than the FM pulse frequency, and having a gate signal input coupled to said other output of said first counter means for enabling said second counter to begin counting clock pulses when said other output is set to said one state and for terminating counting in response to said other output changing to its other state,

processor means and a data bus and an address bus coupled thereto,

decoder means coupled to said data and address buses and having a plurality of output means coupled to said first counter means and said second counter means, respectively,

said second counter means also being coupled to said address and data buses, and

a look-up table coupled to said address and data buses, said look-up table storing digital data in addressable locations corresponding in value, respectively, to digitized analog voltage values,

said decoder responding to a signal from said processor to start a sampling interval by initializing said first counter means and enabling said second counter to count clock pulses during the sampling interval as determined by occurrence of the corresponding edge of the last in said predetermined number of FM pulses in a sampling interval, the digital count in said second counter at the end of the sample corresponding to FM pulse frequency and, hence, to the analog input voltage magnitude during each sampling interval,

said digital counts being read by said processor means by way of said data bus, and said processor means, using said count as an address to a look-up table location for obtaining a digital value corresponding to the FM pulse frequency and the analog input voltage during the respective sampling intervals.