Audio signal recognition computer

• US 4,412,098 A
• Filed: 03/30/1981
• Issued: 10/25/1983
• Est. Priority Date: 09/10/1979
• Status: Expired due to Term

• Current Assignee: GTE Wireless Service Corporation (Verizon Communications Inc.)
• Original Assignee: Interstate Electronics Corp. (L3Harris Technologies, Inc.)
• Inventors: An, Byung H.
• Primary Examiner(s): KEMENY, EMANUEL
• Application Number:
  US06/249,296
• Time in Patent Office: 939 Days
• Field of Search: 179/1 SD, 179/1 SM, 179/1 J, 179/15.55 R, 179/15.55 T, 340/146.3 MA, 364/200 MS File, 364/ 900 MS File, 364/513
• US Class Current: 704/236
• CPC Class Codes: G10L 15/285 Memory allocation or algorithm optimisation to reduce hardware requirements
• CPC Class Codes: G10L 25/87 Detection of discrete points within a voice signal

Abstract

A signal encoder and classifier particularly adapted to speech recognition includes a buffer which is independently addressed by a new data writing address system and a buffered data reading system so that writing and reading of data may be accomplished on a time shared basis. This time shared operation permits serial writing and reading of the pattern data without interrupting income signal storage. The reading data address system utilizes stored addresses identifying the beginning and end of the signal patterns for addressing sequential patterns from the buffer.

Claims

1. Apparatus for identifying signal patterns by comparing plural data elements identifying such patterns with plural data elements identifying a stored reference pattern, comprising:

a first buffer storing said plural data elements identifying signal patterns;

a second buffer storing said plural data elements identifying a reference pattern;

a first register for storing locations in said first buffer at which said plural data elements identifying signal patterns begin;

a second register for storing locations in said first buffer at which said plural data elements identifying signal patterns end;

first addressing means for writing plural data elements identifying said signal pattens into said first buffer, in sequential order, as said plural data elements are received;

means for determining whether said first buffer contains the plural data elements for a complete signal pattern;

second addressing means responsive to said determining means for reading plural data elements identifying said signal patterns from said first buffer at a time when the plural data elements for a complete signal pattern are stored in said first buffer, said second addressing means operating in response to the locations stored in said first and second registers, said reading performed on a time shared basis time independently from said writing operation performed by said first addressing means such that the new writing operations do not have to be delayed until previously written data is read and compared with said reference patterns; and

means for comparing said plural data elements read by said second addressing means with data elements stored in said second buffer.

2. Apparatus for identifying signal patterns as defined in claim 1 wherein said second addressing means further comprises:

second means for comparing the address of said first buffer at which a data element is being read with said second register; and

means responsive to said second comparing means for addressing the data elements of a new signal pattern in said first buffer.

3. Apparatus for identifying signal patterns as defined in claim 1, additionally comprising:

means for returning said first addressing means to the first location in said first buffer when said first addressing means reaches the last location in said first buffer.