Semiconductor integrated circuit and wiring method
First Claim
1. A semiconductor integrated circuit having a top side of overlapped wiring layers, each layer having a respective minimum wiring pitch, said circuit comprising:
- connection wirings formed on respective ones of said overlapped wiring layers, and spaced in accordance with a grid having square meshes with an interval which is larger than a length corresponding to a minimum dimension for patterning in a manufacturing process for making said integrated circuit and corresponding to the respective wiring pitches of the overlapped wiring layers, said respective wiring pitches being expressed by a maximum integer unit which is not a prime number; and
circuit cells respectively connected to corresponding ones of said connection wirings, said circuit cells having vertical and horizontal dimensions corresponding to respective integer multiples of said interval, and terminals spaced in accordance with said grid, for connection to corresponding ones of said connection wirings.
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Abstract
A large scale semiconductor integrated circuit and its wiring method employing a grid system where the layout space is partitioned in the form of a grid by vertical and horizontal line group having an interval larger than a length corresponding to a minimum dimension for a patterning in a manufacturing process; wiring patterns for making connection between each cell which is a unit of layout are depicted on such vertical and horizontal lines; and wirings are made on the basis of the wiring patterns. An interval (d) of these vertical and horizontal lines of the grid is the greatest common factor of the minimum wiring pitches of several overlapped wiring layers and is selected to a dimension which is smaller than said wiring pitch; and the vertical and horizontal line patterns are depicted on the vertical and horizontal lines having the same interval. The vertical and horizontal dimensions of the cell are an integer multiple of the interval (d) of the grid and cell terminals are disposed in an allowable wiring locations on the grid.
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Citations
13 Claims
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1. A semiconductor integrated circuit having a top side of overlapped wiring layers, each layer having a respective minimum wiring pitch, said circuit comprising:
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connection wirings formed on respective ones of said overlapped wiring layers, and spaced in accordance with a grid having square meshes with an interval which is larger than a length corresponding to a minimum dimension for patterning in a manufacturing process for making said integrated circuit and corresponding to the respective wiring pitches of the overlapped wiring layers, said respective wiring pitches being expressed by a maximum integer unit which is not a prime number; and circuit cells respectively connected to corresponding ones of said connection wirings, said circuit cells having vertical and horizontal dimensions corresponding to respective integer multiples of said interval, and terminals spaced in accordance with said grid, for connection to corresponding ones of said connection wirings. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A method for wiring a semiconductor integrated circuit having a top side of overlapped wiring layers, each layer having a minimum wiring pitch, said method comprising the steps of:
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(a) partitioning the top side in the form of a grid with a vertical line group and a horizontal line group, the lines of the vertical and horizontal line groups having an interval larger than a length corresponding to a minimum dimension for patterning in a manufacturing process; (b) positioning circuit cells of the integrated circuit in accordance with the grid, each cell having dimensions corresponding to respective integer multiples of the interval; (c) forming wiring patterns for connection between the cells spaced in accordance with the vertical and horizontal lines, the vertical and horizontal wiring patterns being formed on the same or a different overlapped wiring layer in accordance with the vertical and horizontal lines having the interval, the interval of the vertical and horizontal lines of the grid being selected to be a dimension corresponding to the greatest common factor of the respective minimum wiring pitches of the overlapped wiring layers, the respective minimum wiring pitches being expressed by a maximum integer unit not a prime number. - View Dependent Claims (8, 9, 10, 11, 12, 13)
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Specification