Microprocessor control circuit

• US 4,412,282 A
• Filed: 12/29/1980
• Issued: 10/25/1983
• Est. Priority Date: 12/29/1980
• Status: Expired due to Fees

• Current Assignee: AG Communication Systems Corp. (Nokia Corporation)
• Original Assignee: GTE Automatic Electric Incorporated
• Inventors: Holden, James R.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US06/220,934
• Time in Patent Office: 1,030 Days
• Field of Search: 364/200 MS File, 179/18 E, 179/18 ES
• US Class Current: 710/100
• CPC Class Codes: G06F 11/10 Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
• CPC Class Codes: G06F 11/2215 to test error correction or detection circuits
• CPC Class Codes: H04M 3/241 for stored program controlled exchanges
• CPC Class Codes: H04Q 3/54533 Configuration data, translation, passwords, databases

Abstract

A control circuit, for use in a telephone switching system, which monitors, controls and transfers data to and from memory, input-output devices and external circuits. A microprocessor operates under control of read-only and random-access memories. It communicates with the external telephone system via bus transceivers and a programmable interrupt controller. The integrity of this circuit is monitored by high reliability data and address parity circuits.

Claims

1. A processor control circuit for use in a computer system operated to generate an interrupt signal, said control circuit comprising:

a processing unit operated to generate a group of internal address, data and control signals;

a master bus transceiver connected to said processing unit;

a system data bus connected to said master bus transceiver;

said master bus transceiver operated in response to a first predetermined pattern of said internal address and control signals to transfer said internal data signals to said system data bus;

a local bus transceiver connected to said system data bus and said processing unit; and

an input-output device connected to said local bus transceiver and said processing unit;

said local bus transceiver operated in response to a second predetermined pattern of said internal address and control signals to transfer data from said system data but to said local bus transceiver;

said input-output device operates in response to a third predetermined pattern of said internal address and control signals to transfer data from said local bus transceiver to said input-output device;

said input-output device further operated in response to a fourth predetermined pattern of said internal address and control signals to transfer data to said local bus transceiver;

said local bus transceiver operated in response to a fifth predetermined pattern of said internal address and control signals to transfer data from said input-output device to said system data bus;

said master bus transceiver operated in response to a sixth predetermined pattern of said internal address and control signals to transfer data from said system data bus to said processing unit;

said input-output device comprising

a programmable interrupt controller connected to said computer system and said processing unit, operated in response to said data from said local bus transceiver to arrange an interrupt recognition sequence;

said programmable interrupt controller further operated in response to said interrupt signal to generate an interrupt received signal;

said processing unit further operated in response to said interrupt received signal to generate an interrupt acknowledge signal;

said programmable interrupt controller further operated in response to said interrupt acknowledge signal and said fourth pattern of internal address and control signals to transfer interrupt identification data to said local bus transceiver.

2. A process control circuit as claimed in claim 1, wherein:

said computer system is further operated to generate an access request signal and a group of external address, data and control signals;

said processing unit is further connected to said computer system via a control signal connection and an access request connection and further operated in response to said access request signal to render said internal address and control signals inoperative by causing them to float;

said master bus transceiver and said system data bus are further connected to said computer system, said master bus transceiver further operated in response to a first predetermined pattern of said external control signals to transfer said internal data from said processing unit to said system data bus;

said master bus transceiver further operated in response to a second predetermined pattern of said external control signals to transfer said external data from said system data bus to said processing unit.

3. A processor control circuit as claimed in claim 1, wherein said input-output device comprises:

routining means connected to said processing unit, operated in response to data from said local bus transceiver to generate a fault control signal;

said processing unit operated in response to said fault control signal to generate a fault detected signal;

said routining means further operated in response to said fault detected signal and said fourth pattern of internal address and control signals to transfer fault identification data to said local bus transceiver.

4. A processor control circuit as claimed in claim 1, wherein said processing unit comprises:

a microprocessor operated to generate said internal address and data signals.

5. A processor control circuit as claimed in claim 4, wherein said processing unit further comprises:

a bus controller, connected to said microprocessor, operated to generate said internal control signals.

6. A processor control circuit as claimed in claim 5, wherein said processing unit further comprises:

a read-only memory, connected to said microprocessor, said bus controller and said master bus transceiver, operated in response to a seventh pattern of said internal address and control signals to transfer data to said microprocessor and said master bus transceiver.

7. A processor control circuit as claimed in claim 5, wherein said processing unit further comprises:

a random-access memory connected to said microprocessor, said bus controller and said master bus transceiver, operated in response to an eighth pattern of said internal address and control signals to transfer data to said microprocessor and said master bus transceiver;

said random-access memory further operated in response to a ninth pattern of said internal address and control signals to receive data from said master bus transceiver.

8. A processor control circuit as claimed in claim 7, wherein:

said random-access memory is further operated in response to a third pattern of said external address and control signals to transfer data to said master bus transceiver;

said random-access memory further operated in response to a fourth pattern of said external address and control signals to receive data from said master bus transceiver.

9. A processor control circuit as claimed in claim 4, wherein said microprocessor is further operated to generate a data transmit signal, said processing unit further comprising:

a data parity circuit connected to said microprocessor, operated in response to detection of odd parity across said internal data transmit signal and said data signals to generate an odd parity bit.

10. A processor control circuit as claimed in claim 4, wherein said microprocessor is further operated to generate a data receive signal, said processing unit further comprising:

a data parity circuit connected to said microprocessor, operated in response to detection of odd parity across said data receive signal and said data signals to prevent generation of a data parity failure bit.

11. A processor control circuit as claimed in claim 4, wherein said processing unit is further operated to generate a data read signal, said processing unit further comprising:

a data parity circuit, operated in response to said data read signal to store said data signals;

said microprocessor operated to process said data signals;

said parity circuit operated in response to detection of odd parity across said stored data signals to prevent generation of a data parity failure signal.

12. A processor control circuit as claimed in claim 4, wherein there is further included:

a master address latch, connected to said microprocessor, operated in response to said address signals from said microprocessor to store said address signals and apply said stored address signals to said master bus transceiver;

a duplicate address latch operated to store said address signals from said microprocessor; and

a parity circuit, connected to said duplicate address latch, operated in response to detection of even parity across said duplicate stored address signals to generate an odd parity bit.