Programmable clock rate generator
First Claim
1. A clock rate generator comprising:
- a counter to which is applied an input clock signal,a memory having an input to which is applied a portion of the output of said counter and an output on at least three output lines,counter reset logic connected to one output line from said memory for resetting the counter,means that are controlled by said counter and are connected to at least two other remaining output lines from said memory, for selecting for an output signal the signal on only one of said remaining output lines from said memory, andmeans that are connected to said selecting means so as to receive the output signal therefrom for combining successive output signals from said selecting means which have the same binary state, whereby the output signal from said combining means has a clocking rate which is an integral fraction of that of the input clock signal, the denominator of said fraction being determined by the number of counts between successive resets of said counter and the numerator being determined by the number of cycles in said output signal between successive resets of said counter.
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Abstract
A clock rate generator is described which can be programmed to provide an output clock rate that is N/M times the rate of a standard clock where N and M are integers. The generator comprises a counter, a programmable memory, reset logic and a clocking control. A standard clock is applied to the counter so that the counter is advanced by one for each clock bit. The output of the counter is connected to the input lines of the programmable memory where a pattern of binary ones and zeros are stored. The output of the programmable memory is applied to the clocking control to combine successive bits of the same polarity. The divisor M is determined by the number of standard clock counts between successive resets of the counter. The multiplier N is determined by the number of output cycles from the clocking control between successive resets of the counter.
30 Citations
15 Claims
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1. A clock rate generator comprising:
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a counter to which is applied an input clock signal, a memory having an input to which is applied a portion of the output of said counter and an output on at least three output lines, counter reset logic connected to one output line from said memory for resetting the counter, means that are controlled by said counter and are connected to at least two other remaining output lines from said memory, for selecting for an output signal the signal on only one of said remaining output lines from said memory, and means that are connected to said selecting means so as to receive the output signal therefrom for combining successive output signals from said selecting means which have the same binary state, whereby the output signal from said combining means has a clocking rate which is an integral fraction of that of the input clock signal, the denominator of said fraction being determined by the number of counts between successive resets of said counter and the numerator being determined by the number of cycles in said output signal between successive resets of said counter. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8)
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9. A clock rate generator comprising:
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a counter to which is applied an input clock signal, a programmable memory having an input to which is applied a portion of the output of said counter and an output on at least three output lines, counter reset logic connected to one output line from said memory for resetting the counter, a reset bit stored at a location in said memory such that it is read out on said first output line when said location is addressed by said counter, and connected to the remaining output lines from said memory, means controlled by said counter for selecting as the output signal from said clock rate generator the signal on only one of said remaining output lines, whereby the output signal from said selecting means has a clocking rate which is an integral fraction of that of the input clock signal, the denominator of said fraction being determined by the number of counts between successive resets of said counter and the numerator being determined by the number of cycles in said output signal between successive resets of said counter. - View Dependent Claims (10, 11, 12, 13, 14, 15)
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Specification