Method of batch-fabricating flip-chip bonded dual integrated circuit arrays

• US 4,416,054 A
• Filed: 09/29/1982
• Issued: 11/22/1983
• Est. Priority Date: 07/01/1980
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Westinghouse Electric Corporation (Paramount Global (f/k/a ViacomCBS Inc.))
• Inventors: Thomas, Richard N., Sopira, Michael M.
• Primary Examiner(s): Ozaki, G.
• Application Number:
  US06/427,333
• Time in Patent Office: 419 Days
• Field of Search: 29/572, 29/576 J, 29/577 C, 29/577 R, 29/583, 29/589
• US Class Current: 438/60
• CPC Class Codes: H01L 2224/13 of an individual bump connector
• CPC Class Codes: H01L 2224/13099 Material
• CPC Class Codes: H01L 2224/13144 Gold [Au] as principal constituent
• CPC Class Codes: H01L 2224/81136 involving guiding structures, e.g. spacers or supporting members
• CPC Class Codes: H01L 2224/81801 Soldering or alloying
• CPC Class Codes: H01L 2225/06513 Bump or bump-like direct electrical connections between devices, e.g. flip-chip connection, solder bumps
• CPC Class Codes: H01L 24/10 Bump connectors bumps on insulating substrates, e.g. chip carriers, H01L23/49816; Manufacturing methods related thereto
• CPC Class Codes: H01L 24/13 of an individual bump connector
• CPC Class Codes: H01L 24/81 using a bump connector
• CPC Class Codes: H01L 25/18 the devices being of types provided for in two or more different subgroups of the same main group of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N
• CPC Class Codes: H01L 27/14881 of the hybrid type
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/01015 Phosphorus [P]
• CPC Class Codes: H01L 2924/01023 Vanadium [V]
• CPC Class Codes: H01L 2924/01033 Arsenic [As]
• CPC Class Codes: H01L 2924/01049 Indium [In]
• CPC Class Codes: H01L 2924/01077 Iridium [Ir]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/30105 Capacitance
• CPC Class Codes: H01L 2924/351 : Thermal stress
• CPC Class Codes: H01L 31/022408 : for devices characterised by at least one potential jump barrier or surface barrier

Abstract

A focal plane array including a first integrated circuit for infrared radiation (IR) detection and a second integrated circuit for signal processing is assembled in a flip-chip structural configuration. Each integrated circuit includes an array of metallic contacts on a surface thereof for interconnection in the flip-chip arrangement. The contact array of the IR detector includes a substantially greater number of contacts than the contact array of the signal processor. Consequently, it is not a prerequisite to precisely align the two integrated circuits in a one-to-one contact relationship for the flip-chip bonding operation therebetween. Thus, each metallic contact of the signal processor may be roughly aligned and bonded to a corresponding group of metallic contacts of the IR detector array without altering significantly the operation of the overall focal plane array as long as at least one metallic contact of the IR detector array is included in each corresponding contact group. As a result of this structural improvement, a method of batch-fabricating a plurality of high-density focal plane arrays may be accomplished quite expeditiously.

Claims

1. A method of batch-fabricating a plurality of high-density flip-chip bonded dual integrated circuit arrays comprising the steps of:

3. The method in accordance with claim 1 wherein the step of fabricating the first integrated circuit includes electroplating at least one metallic material on the surface of the first integrated circuit at each cell injection region to provide the first array of metallic cell contacts.

4. The method in accordance with claim 1 wherein the step of fabricating the second integrated circuit includes electroplating at least one metallic material at each of the second array geometric positions on the surface of the second side of the second integrated circuit to provide the second array of metallic detector contacts.

5. The method in accordance with claim 1 wherein the step of bonding includes thermal compression bonding each metallic cell contact of the first integrated circuit with its corresponding group of metallic detector contacts of the second integrated circuit, concurrently, to render the dual integrated circuit flip-chip configuration.

6. The method in accordance with claim 1 wherein the step of dividing includes the steps of:

providing a mechanical support for the bonded dual integrated circuit flip-chip configuration;

predefining each of the plurality of dual integrated circuit arrays;

physically sectioning said predefined circuit arrays from each other; and

removing said sectioned plurality of predefined circuit arrays from their mechanical support.

7. The method in accordance with claim 1 wherein the step of dividing further includes the steps of:

disposing the bonded dual integrated circuit flip-chip configuration on the surface of a flat support member;

flowing a material, which is liquid at temperatures above a first temperature, between the dual integrated circuits of the flip-chip configuration and between the configuration and said flat support member at temperatures above said first temperature;

allowing said material to cool below said first temperature and become solid to provide a mechanical support for the bonded dual integrated circuit configuration;

predefining each of the plurality of dual integrated circuit arrays in accordance with predetermined physical dimensions thereof;

cutting the predefined circuit arrays away from each other along said predetermined physical dimensions; and

removing said material from said cut-away circuit arrays to release them from their mechanical support.

8. The method in accordance with claim 6 wherein the step of cutting includes sawing apart the predefined flip-chip circuit arrays along theie predetermined dimensions.

9. The method in accordance with claim 6 wherein the step of removing the material includes cleaning the material from the surfaces of the cut-away circuit arrays to release them from their mechanical support.

2. fabricating a first integrated circuit for signal processing having a first array of electrical signal storage cells with an injection region and a metallic cell contact disposed at each cell;

fabricating a second integrated circuit for radiation detection having a substrate with a first side conditioned for accepting a radiation image thereon, and a second side, opposite said first side, including a second array of metallic detector contacts disposed on the surface thereof, said second array being fabricated with a greater density of contacts than said first array for substantially equal surface areas, each metallic detector contact being fabricated of a physical size which is smaller than said metallic cell contacts;

bonding each metallic cell contact of said first integrated circuit to a corresponding group of metallic detector contacts of said second integrated circuit to render a dual integrated circuit flip-chip configuration; and

dividing the bonded dual integrated circuit flip-chip configuration into a plurality of high-density dual integrated circuit flip-chip bonded predetermined arrays.