Phase weighted adaptive processor

• US 4,417,249 A
• Filed: 09/08/1980
• Issued: 11/22/1983
• Est. Priority Date: 09/08/1980
• Status: Expired due to Term

• Current Assignee: Sperry Corporation (Unisys Corporation)
• Original Assignee: Sperry Corporation (Unisys Corporation)
• Inventors: Zscheile, John W. Jr.
• Primary Examiner(s): Blum, Theodore M.
• Application Number:
  US06/184,741
• Time in Patent Office: 1,170 Days
• Field of Search: 343/100 LE, 343/100 CL, 455/278, 455/296
• US Class Current: 342/379
• CPC Class Codes: H01Q 3/2623 composed of two antennas

Abstract

Undesirable signals which are similar to desirable signals occur in transmitter-receiver systems, phased array antenna systems and null or steering antenna systems and are eliminated by a novel adaptive processor. The undesired signal is electronically cancelled by causing the weak undesired replica signal to track the stronger undesired reference signal. The circuitry structure employs a phase tracking loop which generates a phase tracking error signal. The phase tracking error signal is applied to a voltage controlled oscillator and a fixed delay element in the phase tracking loop path. The phase tracking loop is coupled to the weak signal path to shift the phase of the weak undesired replica signal so that it is in phase with the stronger undesired reference signal and may be electronically cancelled. The system may be employed to eliminate undesired signals and leave weak desired signals uneffected and easily detectable.

Claims

1. An adaptive processor system of the type employed to eliminate undesired signals, comprising:

a first signal path having an undesirable reference signal thereon,

a second signal path having an attenuated and delayed replica of said undesired reference signal thereon, which is processed to track said reference signal,

a phase tracking feedback path connected in parallel with said second signal path and adapted to shift the phase of said attenuated and delayed replica of said undesired reference signal in said second path to equal the phase of said reference signal,

said phase tracking feedback path comprising therein, a voltage controlled oscillator and a delay coupled to the output of said voltage controlled oscillator,

the output of said delay being phase shifted as a function of the frequency of said voltage controlled oscillator to provide a phase shifted oscillator output signal, and

means in said second signal path for coupling said oscillator output signal and said phase shifted oscillator output signal to the attenuated and delayed replica of said reference signal to provide a phase shifted attenuated and delayed replica signal in phase with said reference signal.

2. An adapted processor as set forth in claim 1 which further includes adjustable attenuation means in said first signal path for attenuating said reference signal.

3. An adaptive processor as set forth in claim 2 wherein said phase tracking feedback path comprises a first mixer coupled to said attenuated reference signal.

4. An adaptive processor as set forth in claim 3 wherein said second signal path comprises a quadrature power splitter for changing the phase of said phase shifted replica signal by ninety degrees,

the ninety degree phase shifted replica signal being subtracted in frequency from said attenuated reference signal in said first mixer of said phase tracking feedback path to provide an error signal output which is coupled to said voltage controlled oscillator to control its frequency output.

5. An adaptive processor as set forth in claim 4 wherein said means for coupling in said second signal path comprises a second mixer having its inputs coupled to the output of said delay and to said attenuated and delayed replica of said reference signal to provide a phase shift and a change in the frequency of said attenuated and delayed replica of said reference signal.

6. An adpative processor as set forth in claim 5 wherein said means for coupling in said second signal path further comprises a third mixer having its inputs coupled to the output of said second mixer and to the output of said voltage controlled oscillator to provide a phase shifted attenuated and delayed replica signal in phase with said reference signal.

7. An adaptive processor as set forth in claim 2 which further includes,

a summing element having its inputs connected to said attenuated reference signal and to said phase shifted attenuated and delayed replica signal for providing an in phase output signal indicative of the amplitude difference of the two input signals.

8. An adaptive processor as set forth in claim 7 wherein said in phase output signal is generated as a positive and/or negative control signal.

9. An adaptive processor as set forth in claim 7 which further includes a fourth mixer having its inputs coupled to the in phase output signal and said phase shifted attenuated and delayed replica signal to provide an output analogue signal proportional to the amplitude difference of said input signals.

10. An adaptive processor as set forth in claim 9 wherein the output of said fourth mixer is coupled to said adjustable attenuation means to provide adjustment of the amplitude of said attenuated reference signal, wherein said attenuated reference signal tracks the amplitude of said phase shifted attenuated and delayed replica signal.

11. An adaptive processor as set forth in claim 10 which further includes a smoothing element intermediate said fourth mixer and said adjustable attenuation means to provide a control signal input to said adjustable attenuation means.

12. An adaptive processor as set forth in claim 11 wherein said smoothing element comprises a low pass filter.

13. An adaptive processor as set forth in claim 7 which further includes an attenuated desired signal in said first and second signal path,

and wherein said attenuated desired signal appears as an output signal at the output of said summing element.