Digital signal processing system

• US 4,417,283 A
• Filed: 07/14/1981
• Issued: 11/22/1983
• Est. Priority Date: 07/17/1980
• Status: Expired due to Fees

• Current Assignee: Sony Corporation (Sony Group Corp.), Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Original Assignee: Sony Corporation (Sony Group Corp.), Tokyo Shibaura Denki Kabushiki Kaisha (Toshiba Corporation)
• Inventors: Kojima, Tadashi, Hoshimi, Susumu
• Primary Examiner(s): Murray, Richard
• Application Number:
  US06/283,240
• Time in Patent Office: 861 Days
• Field of Search: 358/310, 358/335, 358/339, 358/146, 358/147, 358/141, 358/93, 358/12, 358/143, 370/85, 375/37
• US Class Current: 386/338
• CPC Class Codes: G11B 20/10527 Audio or video recording; Data buffering arrangements G11B20/12 - G11B20/18 take precedence
• CPC Class Codes: G11B 20/1208 for continuous data, e.g. digitised analog information signals, pulse code modulated [PCM] data
• CPC Class Codes: G11B 2020/10537 Audio or video recording
• CPC Class Codes: G11B 2020/10546 specifically adapted for audio data
• CPC Class Codes: G11B 2220/90 Tape-like record carriers
• CPC Class Codes: G11C 5/066 Means for reducing external access-lines for a semiconductor memory clip, e.g. by multiplexing at least address and data signals

Abstract

A digital signal processing system in which the actual signal data obtained through digitalization of the information signal and control data of the digital control signals are used for the control of the actual signal data and are transmitted together with a sync signal between two circuits wherein the control data are provided to at least part of an actual signal data transmission line for transmitting the various data and the control data are transmitted during the period of absence of an actual signal data on the transmission line or during the period of the sync signal.

Claims

1. A circuit arrangement for processing analog audio data into a format for transmitting, receiving and playing back in a video format comprising, an analog to digital converter receiving said analog audio data, a large scale integration circuit with clock, read-write, input, output, chip select, data and address terminals, receiving the output of said analog to digital converter, a random access memory connected to said read-write, data and address terminals of said large scale integration circuit, a first tri-state buffer attached to supply outputs to certain of said data terminals of said large scale integration circuit and receiving an input from one of said chip select terminals and a first plurality of switches connected to said first tri-state buffer.

2. A circuit arrangement according to claim 1 wherein said first tri-state buffer can take a high or low state depending upon the positions of said first plurality of switches.

3. A circuit arrangement according to claim 2 wherein said first tri-state buffer can take a floating state when it receives an input from said one chip select terminal.

4. A circuit arrangement according to claim 3 including an oscillator which supplies clock inputs to said large scale integration circuit and to said analog to digital converter.

5. A circuit according to claim 4 including a second tri-state buffer connected to certain of said data terminals and a chip select terminal of said large scale integration circuit and a microcomputer connected to said second tri-state buffer.

6. A circuit according to claim 5 including a playback input terminal which receives a playback signal, a sync separator connected to said playback input terminal, a first dubbing input switch connected to said sync separator, said oscillator and to said clock terminal of said large scale integration circuit, a playback large scale integration circuit receiving an output of said sync separator and a second random access memory connected to said playback large scale integration circuit.

7. A circuit according to claim 6 including a second dubbing/input switch connected to said analog to digital converter, to said playback large scale integration circuit and to the input terminal of said large scale integration circuit.

8. A circuit according to claim 7 including a third dubbing/input switch connected to said oscillator to change the frequency of the clock signal to said large scale integration circuit for NTSC and PAL television signal formats.

9. A circuit according to claim 7 including a latch circuit connected to said playback large scale integration circuit, and a second microcomputer connected to said latch circuit.

10. A circuit according to claim 9 including a third tri-state buffer with a plurality of switches connected to said second random access memory and said playback large scale integration circuit.

11. A circuit according to claim 10 including a buffer connected to said playback large scale integration circuit to said third tri-state buffer, to said latch circuit and to said second microcomputer.