Manual reset control circuit for microprocessor controlled washing appliance

• US 4,418,398 A
• Filed: 06/10/1982
• Issued: 11/29/1983
• Est. Priority Date: 09/04/1979
• Status: Expired due to Fees

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Hornung, Richard E.
• Primary Examiner(s): Zache, Raulfe B.
• Assistant Examiner(s): Eng, David Y.
• Application Number:
  US06/387,134
• Time in Patent Office: 537 Days
• Field of Search: 364/200, 364/900, 364/400, 364/141, 364/143, 364/146
• US Class Current: 713/100
• CPC Class Codes: D06F 2101/00 User input for the control of domestic laundry washing machines, washer-dryers or laundry dryers
• CPC Class Codes: D06F 2105/08 Draining of washing liquids
• CPC Class Codes: D06F 34/08 Control circuits or arrangements thereof
• CPC Class Codes: D06F 34/28 Arrangements for program selection, e.g. control panels therefor; Arrangements for indicating program parameters, e.g. the selected program or its progress
• CPC Class Codes: G05B 19/0426 Programming the control sequence
• CPC Class Codes: G05B 19/0428 Safety, monitoring G05B19/0423 takes precedence
• CPC Class Codes: G05B 2219/25371 Recharge apparatus with material, only when needed or during specific time
• CPC Class Codes: G05B 2219/25381 Restart program at predetermined position, crash recovery after power loss

Abstract

A control circuit is disclosed for appliances such as dishwashers and clothes washers employing a microprocessor programmed to respond to user selected options to determine the operating sequence of the appliance. The control circuit includes a manually operable switch which when actuated generates a reset signal which interrupts or cancels appliance operation by resetting the microprocessor and additionally generates an initiating signal which when detected by the microprocessor following reset, causes the microprocessor to initiate a drain cycle to remove any water present in the appliance as part of the reset program routine.

Claims

1. In a washing appliance having means for performing a plurality of operating functions including a drain function, a control circuit adapted for energization from an external power supply, said control circuit comprising:

a microprocessor for controlling said plurality of function performing means to provide a plurality of operating modes including a drain mode in which the drain function is performed, and an idle mode in which no operating functions are performed, said microprocessor including a reset port and an input port, said microprocessor being constructed and arranged to assume a reset state thereby interrupting appliance operation, whenever a reset signal is present at its reset port at any time during appliance operation;

means for generating an internal reset signal of limited duration and applying said internal reset signal to said reset port in response to restoration of power from the external supply following an interruption thereof;

manually operable reset switch means having an actuated state and a deactuated state;

means for generating a manual reset signal responsive to said reset switch means and operative to apply said manual reset signal to said reset port when said reset switch means is in its actuated state and to remove said manual reset signal when said reset switch means resumes its deactuated state;

means for generating an initiating signal in response to said manual reset signal and operative to maintain said initiating signal at said input port for a predetermined period following removal of said manual reset signal from said reset port;

said microprocessor being further constructed and arranged to scan said input port for the presence of an initiating signal following removal of a reset signal from its reset port and operative to initiate a first predetermined one of said operating modes if said initiating signal is detected and to initiate a second predetermined one of said operating modes otherwise;

whereby in response to a manual reset appliance operation is interrupted and a first predetermined one of the operating modes is initiated and in response to an internal reset, a second predetermined one of the operating modes is initiated.

2. A control circuit in accordance with claim 1 wherein said first predetermined operating mode is said drain mode.

3. A control circuit in accordance with claim 1 wherein said second predetermined operating mode is said idle mode.

4. A control circuit in accordance with claim 1 wherein said first predetermined operating mode is said drain mode and said second predetermined operating mode is said idle mode.

5. A control circuit in accordance with claim 1 or claim 4 wherein said manual reset signal generating means comprises:

first latch means having an input coupled to said manual reset switch means, a first output state for said first latch means being enabled when said switch means is in said actuated state, said first output state defining said manual reset signal.

6. A control circuit in accordance with claim 5 wherein said initiating signal generating means comprises a second latch means having an input coupled to the output of said first latch means, the output state of said second latch means following the output state of said first latch means delayed in time by a predetermined period, the first output state of said second latch means defining said initiating signal.

7. The control circuit in accordance with claim 6 further comprising means for generating a series of clock pulses equally spaced in time, the time between successive pulses defining a control interval, said clock pulse generating means being coupled to said first and second latch means for synchronizing operation of said first and second latch means with said clock pulses.

8. The control circuit in accordance with claim 7 wherein a change in state of said reset switch means enables a change in the output state of said first latch means and the first occurring clock pulse following said change of state of said reset switch means is effective to change the output state of said first latch means, and wherein a change in the output state of said first latch means enables said second latch means to change its output state, and the clock pulse succeeding said first occurring clock pulse is effective to change the output state of said second latch means whereby the output state of said second latch means follows the output state of said first latch means by a predetermined time period equal to one control interval.

9. A control circuit in accordance with claim 7 wherein deactuation of said reset switch means enables said first latch means to assume a second output state and the first occurring clock pulse following deactuation of said reset switch means is effective to place said first latch means in its second output state, thereby removing said manual reset signal from said reset port and the second output state of said first latch means enables said second latch means to assume its second output state and the clock pulse succeeding said first occurring clock pulse is effective to place said second latch means in its second output state, thereby removing said initiating signal from said input port, whereby the initiating signal remains at said input port for a period of time equal to one control interval following removal of said manual reset signal from said reset port.