Hardware for extending microprocessor addressing capability

• US 4,419,727 A
• Filed: 06/01/1981
• Issued: 12/06/1983
• Est. Priority Date: 01/02/1979
• Status: Expired due to Term

• Current Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Original Assignee: Honeywell Information Systems, Inc. (Honeywell International Inc.)
• Inventors: Miller, Robert C., Holtey, Thomas O.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US06/269,502
• Time in Patent Office: 918 Days
• Field of Search: 364/200 MS File, 364/900 MS File
• US Class Current: 711/206
• CPC Class Codes: G06F 12/06 Addressing a physical block of locations, e.g. base addressing, module addressing, memory dedication G06F12/08 takes precedence
• CPC Class Codes: G06F 12/0615 Address space extension

Abstract

A paging apparatus for improved mapping of virtual addresses to real addresses, addressing physical devices coupled to various communication buses, and controlling flow of data. By means of an eight-bit addressing apparatus activated for certain instructions which normally can address only 256 locations, an additional 512 locations can typically be addressed by generating control signals to modify a virtual address into a real address capable of addressing the additional locations. Additionally, the apparatus can control flow of data by enabling or disabling data control apparatus.

Claims

1. In a computer system having at least one microprocessor, a plurality of address modification registers, and a memory having memory locations addressed by real addresses, said memory containing instruction words executable by said microprocessor, some of said instruction words being short type instruction words having shorter address fields than others of said instruction words and being capable of addressing a first number of said memory locations which is less than the total number of locations in said memory, an apparatus for extending the addressing capability of said short type instruction words comprising:

(a) means for detecting whether an instruction word currently being executed by said microprocessor is a short type instruction word;

(b) signal generating means activated by said detecting means and when said detecting means indicates that said instruction word currently being executed is a short type instruction word, said signal generating means generating a predetermined number of control signals; and

(c) first means coupled to said signal generating means and to said address modification registers, said first means responding to said control signals and to data stored in said address modification registers to convert said address fields of said short type instructions being executed by said microprocessor into real addresses for addressing said memory locations in said memory, the number of real addresses which can be formed by said first means being greater than said first number of memory locations.

2. The apparatus as recited in claim 1 wherein said signal generating means includes a programmable read only memory (PROM).

3. The apparatus as recited in claim 1 including a universal synchronous asynchronous receiver transmitter (USART) and further including second means coupled to said first means and to said control signals for using said real address to address said USART and said memory simultaneously.

4. In a computer system having at least one microprocessor, a plurality of address modification registers containing address modification data, and a memory addressed by real addresses, said memory containing instruction words executable by said microprocessor, some of said instruction words being short type instruction words having shorter address fields than others of said instructions, said short type instruction words being capable of addressing a first number of said memory locations which is less than the total number of locations in said memory, an apparatus for extending the addressing capability of said short type instruction words comprising:

(a) gating means for enabling the exchange of address modification data between said address modification registers and said microprocessor;

(b) means for detecting whether an instruction word currently being executed by said microprocessor is a short type instruction word;

(c) signal generating means activated by said detecting means when said detecting means indicates that said currently-executed instruction word is a short type instruction word, said signal generating means generating a predetermined number of control signals; and

(d) first means coupled to said signal generating means and to said address modification registers, said first means responding to said control signals and to said address modification data to convert said address fields of said short type instructions being executed by said microprocessor into real addresses for addressing said memory locations in said memory, the number of real addresses which can be formed by said first means being greater than said first number of locations in said memory.

5. The apparatus as recited in claim 4 wherein said signal generating means is a programmable read only memory (PROM).

6. The apparatus as recited in claim 5 wherein said gating means includes a bus-driver.

7. The apparatus recited in claim 4 including a universal synchronous asynchronous receiver transmitter (USART) and further including second means coupled to said first means and to said control signals for using said real addresses to address said USART and said memory simultaneously.

8. In a computer system having a microprocessor, a plurality of address modification registers, and a memory having memory locations addressed by real addresses, said memory containing instruction words executable by said microprocessor, some of said instruction words being short type instruction words having address fields shorter than others of said instruction words and being capable of addressing a first number of said memory locations which is less than the total number of locations in said memory, a method for extending the addressing capability of said short type instruction words comprising the steps of:

(a) forming real addresses by modifying said address fields of said instruction words only when said microprocessor is executing said short type instruction words, the number of locations which can be accessed by said real addresses being greater than said first number of locations; and

(b) using said real addresses to access locations in said memory.

9. The method of claim 8 wherein the step of forming said real addresses includes the steps of:

(a) generating control signals when said microprocessor is executing short type instruction words;

(b) using said control signals to form certain bits of said real addresses; and

(c) using the bits of said address fields as the bits of said real addresses which were not formed by said control signals.

10. The method of claim 9 wherein the step of generating signals includes the steps of:

(a) activating a signal generating means when said microprocessor is executing said short type instructions; and

(b) generating said signals from said signal generating means based upon certain bits in said address field.

11. The method of claim 10 wherein the step of using said signals to form certain bits of said real address includes the steps of:

(a) using said control signals to place the contents of certain of said address modification registers into certain bits of said real address, and

(b) using said signals to place constant data into certain other bits of said real address.

12. In a computer system having a microprocessor, a plurality of address modification registers, a universal asynchronous receiver transmitter (USART) for exchanging data with said microprocessor, and a memory having memory locations addressed by real addresses, said memory containing instruction words executable by said microprocessor, some of said instructions being short type instruction words having address fields shorter than others of said instruction words and being capable of addressing a first number of said memory locations which is less than the total number of locations in said memory, a method for extending the addressing capability of said short type instruction words comprising the steps of:

(a) forming real addresses by modifying said address fields of said instructions only when said microprocessor is executing said short type instruction words, the number of real addresses which can be formed being greater than said first number of locations; and

(b) using said real addresses to address locations in said memory and to address said USART simultaneously, and thereby to store in said memory the data exchanged with said USART.

13. The method of claim 12 wherein the step of forming said real addresses includes the steps of:

(a) activating a signal generating means when said microprocessor is executing said short type instruction words;

(b) generating control signals from said signal generating means based upon certain bits in the address fields of said short type instruction words;

(c) using said control signals to place the contents of certain of said address modification registers into certain bits of said real addresses;

(d) using said control signals to place constant data into certain other bits of said real addresses; and

(e) using the bits of said address fields of said short type instruction words to form those bits of said real addresses into which data were not placed by said control signals.