Method of fabricating mesa MOSFET using overhang mask

• US 4,419,811 A
• Filed: 04/26/1982
• Issued: 12/13/1983
• Est. Priority Date: 04/26/1982
• Status: Expired due to Fees

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Acrian, Inc.
• Inventors: Rice, Edward J.
• Primary Examiner(s): Ozaki, George T.
• Application Number:
  US06/371,599
• Time in Patent Office: 596 Days
• Field of Search: 29/571, 29/578, 29/579, 29/580, 29/591, 148/187, 357/23 VD, 357/55
• US Class Current: 438/268
• CPC Class Codes: H01L 29/41741 for vertical or pseudo-vertical devices
• CPC Class Codes: H01L 29/41766 with at least part of the source or drain electrode having contact below the semiconductor surface, e.g. the source or drain electrode formed at least partially in a groove or with inclusions of conductor inside the semiconductor H01L29/41733 - H01L29/41758 take precedence
• CPC Class Codes: H01L 29/7801 DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region lateral high-voltage MISFETs with channel well and drain offset region H01L29/7835
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7816 Lateral DMOS transistors, i.e. LDMOS transistors

Abstract

A mesa structure field effect transistor includes a semiconductor body with at least one mesa formed on a major surface and an insulating layer on the mesa and overhanging the mesa. Doped regions in the side walls of the mesa define the channel region and source of the transistor, and the semiconductor body defines the drain region. Preferential etching techniques are employed in forming the mesas and the overhanging insulator. The overhanging insulator is employed as a shadow mask in fabricating the transistor.

Claims

1. A method of fabricating a field effect transistor in a body of semiconductor material of first conductivity type comprising the steps of

(a) forming a plurality of spaced layers of insulating material on a major surface of said body constituting a common drain region,

(b) forming regions of opposite conductivity type in said major surface by introducing dopants into exposed portions of said major surface of said semiconductor body,

(c) removing a portion of said region of opposite conductivity by chemical etching thereby forming mesa structures with said spaced layers of insulating material overhanging said mesas,

(d) diffusing a dopant of said first conductivity type into the etched surface of said regions of opposite conductivity type,

(e) applying a preferential etchant to said etched surface thereby removing said dopant of said first conductivity type except in the side walls of said mesas to form source regions, and

(f) forming conductive metal layers on said plurality of spaced layers to form gate electrodes and conductive layers on said etched surfaces to form source electrodes, said spaced layers overhanging said mesas interrupting said conductive metal layers on said spaced layers from said conductive layers on said etched surface.

2. A method of fabricating a field effect transistor in a body of semiconductor material of first conductivity type comprising the steps of

(a) forming a plurality of spaced layers of insulating material on a major surface of said body constituting a common drain region,

(b) removing at least a portion of said major surface of said semiconductor body by chemical etching thereby forming mesa structures on said major surface with said spaced layers of insulating material overhanging said mesas,

(c) forming regions of opposite conductivity in said major surface by introducing dopants into the etched portions of said major surface,

(d) diffusing a dopant of said first conductivity type into the etched surface of said regions of opposite conductivity type,

(e) applying a preferential etchant to said etched surfaces thereby removing said dopant of said first conductivity type except in the side walls of said mesas to form source regions, and

(f) forming conductive metal layers on said plurality of spaced layers to form gate electrodes and conductive layers on said etched surfaces to form source electrodes, said spaced layers overhanging said mesas interrupting said conductive metal layers on said spaced layers from said conductive layers on said etched surfaces.

3. A method of fabricating a field effect transistor in a body of semiconductor material of first conductivity type comprising the steps of

(a) forming a plurality of spaced layers of insulating material on a major surface of said body constituting a common drain region,

(b) forming regions of opposite conductivity type in said major surface by introducing dopants into exposed portions of said major surface of said semiconductor body,

(c) removing a portion of said regions of opposite conductivity by chemical etching thereby forming mesa structures with said spaced layers of insulating material overhanging said mesas,

(d) oxidizing the etched surfaces of said semiconductor body, thereby forming silicon oxide layers,

(e) depositing masking material layers on said plurality of spaced layers and on said etched surfaces, said spaced layers overhanging said mesas interrupting said masking material layer on said spaced layers from said layers on said etched surface,

(f) removing the silicon oxide on the side walls of said mesa not covered by said masking material layer under said overhanging spaced layers,

(g) removing said masking material layers,

(h) diffusing a first conductivity type dopant into the exposed surfaces of said mesa side walls to form source regions,

(i) removing said silicon oxide layers from said etched regions, and

(j) forming conductive metal layers on said plurality of spaced layers to form gate electrodes and conductive layers on said etched surfaces to form source electrodes, said spaced layers overhanging said mesas interrupting said conductive metal layers on said spaced layers from said conductive metal layers on said etched surface.

4. The method of fabricating a field effect transistor as defined by claim 3 and further including the step of etching the exposed side wall surfaces following step (f) and before step (g).